Applied Micro Circuits Corporation

Infineon Technologies Ag

Ampere Computing LLC

Qimonda Ag

Luca Ravezzi

Hamid Partovi

Alfred Yeung

Karthik S Gopalakrishnan

Yan Chong

John Ngai

John Gregory Favor

Matthew Ashcraft

Edoardo Prete

Paul Georg Lindt

David S Oliver

Russell Homer

Sivaraman Chokkalingam

Andreas Blum

Qawi Harvard

Matthew W Ashcraft

Various aspects provide for mitigating voltage droop associated with a microprocessor (e.g., by controlling a clock associated with the microprocessor). For example, a system can include a microprocessor and a controller. The microprocessor can receive a clock provided by a clock buffer. The controller can control frequency of the clock provided by the clock buffer based on a voltage associated with the microprocessor. In an aspect, the controller can reduce the frequency of the clock in response to a determination that the voltage satisfies a defined criterion. Additionally, the controller can incrementally increase the frequency of the clock in response to another determination that the voltage satisfies another defined criterion after satisfying the defined criterion.

Clock control based on voltage associated with a microprocessor

Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a power distribution network of an integrated circuit to a second supply voltage via a resistance ladder circuit. The comparator component can generate a comparison output signal in response to a determination that a comparison between the second supply voltage and a reference voltage satisfies a defined criterion.

Variation immune on-die voltage droop detector

A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.

Self-referenced on-die voltage droop detector

Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device.

High frequency voltage supply monitor

Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a pre-charge stage, a second keeper, a post-dissipation stage, and a third keeper. The second keeper maintains a first binary value in a slave pass mode when the mDb signal has a second binary value. The second keeper supports the second binary value in the slave pass mode when the mDb signal has the first binary value. The third keeper maintains the Q signal binary value during the slave hold mode.

Pseudo single-phase flip-flop (PSP-FF)

A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a Dsignal, an input to accept a clock signal, an input to accept an inverted shadow-Dsignal, and an output to supply a Dsignal. The master latch has an input to accept a shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Dsignal and the inverted shadow-Dsignal. The slave latch has an input to accept the Dsignal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the Dsignal or the shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.

Hazard-free minimal-latency flip-flop (HFML-FF)

A system is provided with a digital complementary-metal-oxide-semiconductor (CMOS) device and a noise cancellation circuit. The CMOS device has a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply a binary logic output signal, and a fourth interface connected to a first dc voltage (e.g., ground) to sink current. A first resistor is interposed between a second dc voltage (e.g., Vdd), with a potential higher than the first dc voltage, and the second interface of the CMOS device. The noise cancellation circuit has a first interface connected to the second dc voltage. The noise cancellation circuit high pass filters ac noise on the second dc voltage, amplifies the filtered noise, and supplies the amplified noise at a second interface connected to the second interface of the CMOS device.

Digital CMOS circuit with noise cancellation

One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.

Integrated circuit including calibration circuit

An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.

Electrical idle detection circuit including input signal rectifier

A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Data sampler including a first stage and a second stage

A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

Clock data recovery circuit with circuit loop disablement

An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.

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San Francisco, CA, United States of America

Luca Ravezzi