Micron Technology Incorporated

Stmicroelectronics S.r.l.

Luca Porzio

Roberto Izzi

Graziano Mirichigni

Danilo Caraccio

Daniele Balluchi

Erminio Di Martino

Christian M Gyllenskog

Stefano Zanardi

Domenico Monteleone

Giacomo Bernardi

Paolo Amato

Marco Dallabora

Nicola Colella

Chee Weng Tan

Andre Klindworth

Marco Onorato

Emanuele Confalonieri

Corrado Villa

Giuseppe D'Eliseo

Alessandro Orlando

Sebastien Lemarie

Jonathan Scott Parry

Giuseppe Cariello

Dionisio Minopoli

Reshmi Basu

Stephen D Hanna

Paolo Papa

Nadav Grosz

Marco Di Pasqua

Ting Luo

Deping He

Christopher Joseph Bueb

Olivier Duval

Antonino Pollio

Ferdinando Pascale

Gianluca Coppola

Ciro Feliciano

Rodolphe Sequeira

Gennaro Schettino

Ryan Laity

David Aaron Palmer

Massimo Iaculo

Francesco Falanga

Yanhua Bi

Rakeshkumar Dayabhai Vaghasiya

Crescenzo Attanasio

Andrea Vigilante

Francesco Basso

Sean L Manion

Massimo Zucchinali

Giuseppe Russo

Bryan D Butler

Antonio Furno

Antonio Iorio

Sebastien LeMarie

Alfredo Palazzo

Methods, systems, and devices for reliable and efficient boot logical unit access are described. For instance, a memory device may receive a request to write data to a boot logical unit of the memory device. The memory device may update a parameter from a first value to a second value based on receiving the request, the second value indicating a first stage of a procedure for updating the boot logical unit. The memory device may write, to a block of memory in the memory device, the data based on the parameter indicating the first stage of the procedure. Additionally or alternatively, the memory device may read a value of the parameter as part of a power up procedure and may perform a boot procedure using either first data at the boot logical unit or second data at the block of memory based on reading the value of the parameter.

Reliable and efficient boot logical unit access

Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.

Write booster buffer and hibernate

Methods, systems, and devices for data block refresh during read access are described. In some instances, when an access command (e.g., a read command) is received, a memory system may determine if the associated block is a PSA block. If the block is PSA block, its data may be provided to a host system to satisfy the read command and the block may either be refreshed or may be designated to be refreshed. For example, the block may be refreshed by copying its data to a write cache and writing the data from the cache to a new block. In other instances, an LBA of the block may be stored (e.g., designated) and the LBA may be refreshed when the memory system is idle.

Data block refresh during read access

Methods, systems, and devices for techniques for data refresh based on environmental conditions are described. A memory system may program data to a set of blocks, where an order in which the data be programmed to respective blocks of the set of blocks may be based on a first block ordering. The memory system may also program respective indications of respective temperatures of the programming for the respective blocks. The memory system may identify, during a start-up procedure, a flag indicating to perform a refresh operation for the set of blocks. As such, the memory system may perform during the start-up procedure, the refresh operation for the set of blocks using a second block ordering. In some examples, the second block ordering may be based on the respective indications of the respective temperatures for the set of blocks.

Techniques for data refresh based on environmental conditions

Methods, systems, and devices for data defragmentation control are described. A memory system may include one or more regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. In some instances, data may be stored to one or more discontinuous physical addresses and it may be desirable rearrange the data to be within continuous physical addresses (e.g., it may be desirable to defragment the data). Accordingly, the data stored to the one or more discontinuous physical addresses may be arranged (e.g., rearranged) to be within continuous physical addresses based at least in part on a value stored to one or more registers of the memory system.

Data defragmentation control

Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Reading sequential data using mapping information stored at a host device

Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.

Determining available resources for storing data

Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Hardware reset management for universal flash storage

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Low-power boot-up for memory systems

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Latency reduction of boot procedures for memory systems

Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.

Dynamic parity scheme

Methods, systems, and devices for copy command for a memory system are described. A method may include storing, within a memory system, data associated with one or more first addresses within an address space. The method may further include receiving a copy command for the data from a host for the memory system. The memory system may associate, in response to the copy command, the data with one or more second addresses within the address space.

Copy command for a memory system

Described are systems and methods for prioritization of background media management operations in memory systems. An example system comprises a controller coupled to a memory array comprising a plurality of memory cells. The controller is configured to perform operations, comprising: identifying a plurality of address ranges referencing respective sets of memory cells of the memory array, wherein each address range is associated with a respective memory access operation counter reflecting a number of memory access operations that have been performed with respect to a corresponding set of memory cells; identifying, among the plurality of address ranges, an address range associated with a maximum value of a corresponding memory access operation counter; and causing a media management operation to be performed with respect to a set of memory cells referenced by the identified address range.

Prioritization of background media management operations in memory systems

Methods, systems, and devices for techniques for controlling command order are described. An entity of a host system, such as a file system, may insert a sequential identifier into commands generated by the entity to indicate an order of the commands. In some examples, the host system may specify a set of commands in a first sequence to be transmitted to the memory system. The host system may subsequently reorder the set of commands in to a second sequence and transmit the set of commands to the memory system. In some cases, following a power-on condition, the memory system may determine a latest valid command of the set of commands. The memory system may subsequently invalidate one or more logical addresses associated with commands having sequence identifiers after the sequence identifier of the latest valid command.

Techniques for controlling command order

Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Commanded device states for a memory system

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Casalnuovo di Napoli, Italy

Luca Porzio