Stmicroelectronics S.r.l.

Cambridge Silicon Radio Limited

Luca Milani

Luigi Colalongo

Anna Richelli

Fabrizio Torricelli

Zsolt Miklos Kovàcs-Vajna

Rainer Herberholz

Roberto Giorgio Bardelli

Justin Penfold

Kwangseok Han

Fausto Carace

Giovanni Lanfranchi

A non-volatile memory includes cells arranged in rows and columns. Each memory cell includes an access portion and a control portion. The access and control portions share an electrically floating layer of conductive material defining a first capacitive coupling with the access portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity lower than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current extracts charge carriers from the electrically floating layer through Fowler-Nordheim tunneling to store a first logic value in the memory cell. The access portion is configured so that an electric current injects charge carriers in the electrically floating layer by injection of band-to-band tunneling-induced hot electrons to store a second logic value, respectively, in the memory cell.

Embedded non-volatile memory with single polysilicon layer memory cells erasable through band to band tunneling induced hot electron and programmable through Fowler-Nordheim tunneling

An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

Antifuse cell with capacitor and transistors

A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.

Embedded non-volatile memory with single polysilicon layer memory cells programmable through channel hot electrons and erasable through fowler-nordheim tunneling

A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.

Embedded non-volatile memory with single polysilicon layer memory cells programmable through band-to-band tunneling-induced hot electron and erasable through fowler-nordheim tunneling

Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.

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Mairano, Italy

Luca Milani