Stmicroelectronics S.r.l.

Luca Giuseppe De Ambroggi

Salvatore Nicosia

Francesco Tomaiuolo

Promod Kumar

Fabrizio Campanale

Luigi Pascucci

Carmelo Condemi

Francesco Pipitone

Salvatore Giove

Gaetano Palumbo

Giovanni Pagano

Pierpaolo Nicosia

Carmelo Condemii

Francesco Tomaiulo

Kumar Promod

Giuseppe Piazza

The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit having a plurality of volatile-memory elements connected through a sequential daisy-chain connection. A nonvolatile memory unit stores, in a nonvolatile way, the redundancy information through a data bus, connected both to the redundancy-detection unit and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit transfers the addresses of the failed data-storage unit to the nonvolatile memory unit for their nonvolatile storage.

Nonvolatile storage device and self-redundancy method for the same

An Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. Test routines are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided) internally without involving any external complex or expensive test equipment to control the test program. The device architecture is transparent from a tester point of view, with a standard interface having a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.

Built-in testing methodology in flash memory

A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Circuit for controlling a reference node in a sense amplifier

A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

ATD generation in a synchronous memory

A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

Stabilized delay circuit

A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode

A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.

Circuit for managing the transfer of data streams from a plurality of sources within a system

A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.

Redundancy architecture for an interleaved memory

An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data

An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.

Interleaved memory device for sequential access synchronous reading with simplified address counters

An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

Accelerated carry generation

An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.

Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit

A data output buffer includes an output node, and a first stage connected to the output node for providing a first control signal for precharging the output node to an intermediate voltage with respect to a voltage for switching the output node from a current logic state to a different logic state. A second stage is connected to the first stage and to the output buffer. The first and second stages are responsive to a second control signal for enabling output of new data. A precharge logic circuit precharges the output node to the intermediate voltage as a function of data last output, and as a function of first and second reset signals until a rising and falling edge of the data last output respectively crosses the intermediate voltage.

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Catania, Italy

Luca Giuseppe De Ambroggi