Stmicroelectronics S.r.l.

Luca Gandolfi

Marco Leo

Marco Castellano

Enrico Rosario Alessi

Fabio Passaniti

Francesco Bruni

A device for monitoring the health state is made in a chip including a semiconductor die integrating an electric potential sensor and a cardiac parameter determination unit. The potential sensor is configured to detect potential variations on the body of a living being and associated with a heart rhythm and to generate a cardiac signal. The cardiac parameter determination unit is configured to receive the cardiac signal and determine cardiac parameters indicative of a health state. In particular, the cardiac parameter determination unit is configured to detect triggering events and to determine features of the cardiac signal in time windows defined by the triggering events. The die also integrates a decision unit, configured to receive the cardiac parameters and generate a health signal based on a comparison with threshold values. The cardiac parameters include heart rate and QRS-complex.

Health state monitoring device and method

System, method, and circuitry for utilizing sequential input inertial sensor data to calculate recursive features for training a machine learning algorithm or for classifying the data as a known class. The recursive feature values of a current data sample are calculating based on comparisons between the current data sample value and previous recursive feature values. The recursive features include a recursive maximum, recursive minimum, recursive peak to peak, recursive average, recursive root mean square, and recursive variance.

Method, system, and circuit for extracting features for use in embedded artificial intelligence mechanisms

A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.

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Milan, Italy

Luca Gandolfi