Alcatel

Nokia Solutions and Networks Oy

Alcatel Lucent

Luca Gabriele Razzetti

Giancarlo Gavioli

Silvio Cucchi

Mario Martinelli

Carlo Costantini

Marianna Pepe

Andreas Leven

Jeremie Renaudier

Stefano Gastaldello

Paolo Sorge

Alberto Bellato

Sergio Cabrini

Stephan Ten Brink

Lucia Marazzi

Paola Galli

Alberto Lometti

Paola Parolari

Laurent Schmalen

Domenico Campi

Giovanni Traverso

Silvano Frigerio

Sonia Rinaldi

Giulio Gladiali

Daniele Cucchi

Sara Caobianco

Carlo Constantini

Antonio Ruggiero

Domenico Marsella

Alessandra Rossi

Claudio Girardi

Roberto Cardillo

Davide Cattaneo

Stephen Lewis

Domenico Di Mola

Luca Suberini

Maurizio Skerlj

Marcello Magna Detto Calceterra

Roberto Manenti

Architectures for inter-converting bitstreams and symbol streams of PAM and/or QAM constellations of different sizes that are not base-2 integers. Some of such constellations may be Gray-coded, and the constellation mapping may be performed to achieve an equiprobable distribution of different constellation symbols. Some embodiments may be compatible with FEC schemes. In an example embodiment, a transmitter DSP may employ a conventional constellation mapper preceded by an electronic encoder programmed to exclude some constellation-symbol labels from the bitstream applied to the mapper. In different embodiments, the electronic encoder may employ a CCDM and/or a long-division operation to select some amplitudes of the constellation and to exclude others. At least some embodiments are beneficially capable of achieving a smaller gap to the Shannon limit than comparable conventional solutions.

Bits-to-symbols mapping for amplitude modulation

A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.

Reduced-power implementation of error-correction processing

An apparatus, comprising: circuitry configured, in response to receipt of input data, to transmit a stream of symbols of a constellation to a modulator for modulation onto a carrier wherein a frequency of occurrence of symbols in the stream is dependent upon a probability-amplitude distribution for symbols of the constellation, wherein the probability-amplitude distribution has a kurtosis less than a target value and a shape of the probability-amplitude distribution causes low-amplitude symbols to occur more frequently on average in the stream than high-amplitude symbols.

Probabilistic amplitude shaping

An apparatus includes a digital signal processor to perform perturbation-based optical nonlinearity compensation of optical data signals of a communication stream. The digital signal processor includes first digital circuits to calculate multiplicative factors for corrections to the optical data signals from products of values of the optical data signals at a reduced set of times. The reduced set is a down-sampling of the sequence of consecutive symbol times of the communication stream. The digital signal processor also includes second digital circuits to calculate the multiplicative factors for corrections to the optical data signals at the consecutive symbol times by interpolating the multiplicative factors evaluated at the reduced set of times.

Digital fiber nonlinearity compensation

It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.

Optical coherent receiver with forward error correction

Proposed is a method of decoding a differentially encoded PSK modulated optical data signal carrying FEC encoded data values. The optical signal is corrected by an estimated phase offset. From the corrected signal, respective likelihood values for the FEC encoded data values are derived, using an estimation algorithm which accounts for a differential encoding rule used for differentially encoding the optical signal. The derived likelihood values are limited to a predetermined range of values. From the limited likelihood values, FEC decoded data values are derived, using an algorithm which accounts for a FEC encoding rule used for FEC encoding the FEC encoded data values.

Method of decoding a differentially encoded phase modulated optical data signal

In a method of demapping a tributary from a first frame into a second frame, the first frame has a plurality of tributary words and a synchronization word, and first and second counters are provided. The first counter is increased by a first value at each dock cycle of the second frame, and reading operations are performed according to the second counter. Synchronization information, generated according to the synchronization word, is used to change between first and second states. When in the first state, the second counter is synchronized to the first counter at each clock cycle of the second frame; and, when in the second state, the second counter is synchronized to the first counter at a predetermined instant of the second frame, the second counter increasing by a second value at each clock cycle of the second frame wherein the reading operation is performed.

Method and device for demapping a tributary recovering lower order synchronism

Disclosed is a device for providing an improved switching from one of two or more working resources to at least one spare resource in a telecommunication apparatus, each of the working resources comprising a profile with a set of parameters and configuration information, wherein the at least one spare resource comprises a bank of profiles, each profile of the bank corresponding to a profile of the working resources, and further comprises means for selecting a profile of the bank so that when a working resource has to be replaced by a spare resource, a profile in the bank corresponding to the profile of the working resource is selected for provisioning the spare resources accordingly. According to an embodiment, the working and spare resources are embodied in ports of a telecommunication apparatus.

Device and method for improving switching time of section/line and equipment protections

Disclosed is a device and method for processing a frame including overhead and payload, the device comprising: a first hardware module for processing the payload, the payload processing comprising termination/adaptation and cross-connection functions; and a second hardware module for processing at least a part of overhead, wherein said second hardware module cooperates with the first hardware module for controlling the payload cross-connection and consequent actions.

Hardware functional partitioning in a system platform of a telecommunication network element

The present invention provides for a method and apparatus for carrying out connection and related input/output processing functions in a Sinchronous Digital Hierarchy (SDH/SONET) transport node (network), in which the payload switching matrices (e.g. MSPC and HPC matrices for an High Order VC system) collapse into one single functional block (MTRX), while the Virtual Container (VCs) monitoring functions (HVC_RX, HVC_TX) are shifted to the Input/Output position of the matrices.

Method and apparatus for carrying out connection and related input/output processing functions in a synchronous digital hierarchy transport node

Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Time division multiplexed link connections between a switching matrix and a port in a network element

A method and circuit are described for improving the pointer processing in the case of synchronous digital hierarchy (SDH) or synchronous optical network (SONET) transmission frames with VC4_4c, VC4_16c and VC4_64c concatenated payloads. The technique proposed by the existing Standards provides for two different state diagrams to be used in the pointer processing algorithm. One state diagram is used in the case of a concatenated payload and the other state diagram is used in the case of a non-concatenated payload. However, no solution is disclosed for automatically going from the states of one diagram to the states of the other diagram. The present invention provides a circuit so constructed that it can be used in an apparatus processing STM-4, STM-16 and STM-64 frames, through which the automatic recognition of the VC4-4c, VC4-16c and VC4-64c payload concatenation can be achieved. Therefore, it is not necessary to configure in advance the concatenation or non-concatenation condition.

Method and circuit for improving the pointer processing in synchronous digital hierarchy (SDH) transmission frames

A method and circuit for mismatch detection in SDH-coded frame trace identifiers within a telecommunication network, wherein received trace identifiers are compared with expected trace identifiers in determined locations of the communication network, to detect if a misconnection event has occurred and generate a corresponding alarm signal. The method comprises the steps of: a) validating the received trace identifier (TI) and issuing a corresponding validation signal (CRC , CNST); b) comparing the received trace identifier (TI) with an expected trace identifier (ETI) and issuing a corresponding validation signal (MTC , MTC ); c) evaluating the validation signal (CRC , CNST) and the match signal (MTC , MTC ); and d) generating a matching state signal (SVAL , SVAL ) according to the result of the evaluation as per step c), wherein steps a) and b) are executed in parallel.

Mismatch detection in SDH frame trace identifiers

Growing community of inventors

Sesto San Giovanni, Italy

Luca Gabriele Razzetti