Micron Technology Incorporated

Other

Intel Corporation

Round Rock Research, LLC

Luca De Santis

Tommaso Vali

Kenneth James Eldredge

Frankie F Roohparvar

Violante Moschiano

Luigi Pilolli

Walter Di Francesco

Pasquale Conenna

Giulio Giuseppe Marotta

Vishal Sarin

Giovanni Santin

Michele Incarnati

Theodore T Pekny

Ramin Ghodsi

Marco-Domenico Tiburzi

Jae-Kwan Park

Ali Mohammadzadeh

Agostino Macerola

Maria Luisa Gallese

Sivagnanam Parthasarathy

Jung Sheng Hoei

Terry M Grunzke

Renato C Padilla

Luca Nubile

Gianfranco Valeri

Vamshi K Indavarapu

Lucia Botticchio

Umberto Siciliani

Giovanni Naso

Pasquale Pistilli

Mauro Castelli

Fernanda Irrera

Umberto Minucci

Giuliano Gennaro Imondi

Andrea Giovanni Xotta

Walter Di-Francesco

Maria-Luisa Gallese

Biagio Iorio

Cristina Lattaro

Fumin Gu

Guido Luciano Rizzo

Emanuele Sirizotti

Tomasso Vali

Yuanhang Cao

Violante Moshciano

Ricardo Cardinali

Maria Gallese

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Apparatuses and methods for concurrently accessing different memory planes of a memory

A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.

Memory devices for comparing input data to data stored in memory cells coupled to a data line

A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

Asynchronous interrupt event handling in multi-plane memory devices

A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

Power budget arbitration for multiple concurrent access operations in a memory device

A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

Checking status of multiple memory dies in a memory sub-system

Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

Memory devices for pattern matching based on majority of cell pair match

The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array, execute the query, and send only the particular data to the host upon executing the query.

Acceleration of data queries in memory

Apparatus including an array of memory cells, and a controller configured to cause the apparatus to determine a first value indicative of a number of memory cells of a plurality of memory cells that are activated in response to a control gate voltage having a particular voltage level, compare the first value to a plurality of second values, and determine an expected data age of the plurality of memory cells or a plurality of read voltages in response to the comparison of the first value to the plurality of second values.

Apparatus for determining an expected data age of memory cells

Memory having a controller configured to cause the memory to determine a respective raw data value of a plurality of possible raw data values for each memory cell of a plurality of memory cells, count occurrences of each raw data value for a first set of memory cells of the plurality of memory cells, store a cumulative number of occurrences for each raw data value, determine a plurality of valleys of the stored cumulative number of occurrences for each raw data value with each valley corresponding to a respective raw data value of the plurality of possible raw data values, and, for each memory cell of a second set of memory cells of the plurality of memory cells, determine a data value for that memory cell in response to the raw data value for that memory cell and the respective raw data values of the plurality of valleys.

Apparatus for determining data states of memory cells

Memories might include control logic configured to cause the memory to perform a first sense operation having an initial phase and a plurality of sensing phases on a first grouping of memory cells, pause the first sense operation upon completion of a present sensing phase in response to receiving a command to perform a second sense operation on a second grouping of memory cells while performing the present sensing phase, perform an initial phase of the second sense operation after pausing the first sense operation, and, in response to completion of the initial phase of the second sense operation, resume the first sense operation at a next subsequent sensing phase of the plurality of sensing phases and continue to a sensing phase of the second sense operation to perform the next subsequent sensing phase of the first sense operation and the sensing phase of the second sense operation concurrently.

Memories configured to perform concurrent access operations on different groupings of memory cells

A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

Memory cells configured to generate weighted inputs for neural networks

The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Partially written block treatment

Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.

Memory devices for pattern matching

Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.

Growing community of inventors

Avezzano, Italy

Luca De Santis