Hitachi Energy Ltd

Abb Power Grids Switzerland Ag

Abb Schweiz Ag

Hitachi Energy Switzerland Ag

Luca De-Michielis

Chiara Corvasce

Munaf Rahimo

Wolfgang Amadeus Vitale

Florin Udrea

Maxi Andenna

Umamaheswara Vemulapati

Marina Antoniou

Neophytos Lophitis

Boni Kofi Boksteen

Elizabeth Buitrago

Uwe Badstuebner

An insulated gate bipolar transistor includes a source electrode, a collector electrode, a source layer, a base layer, a drift layer and a collector layer. Trench gate electrodes extend through the base layer into the drift layer. A channel is located between the source layer, the base layer and the drift layer. A trench Schottky electrode is adjacent to one of the trench gate electrodes and includes an electrically conductive Schottky layer arranged lateral to the base layer and extends through the base layer into the drift layer. The Schottky layer is electrically connected to the source electrode. Collection areas are located in the drift layer at a respective trench gate electrode bottom of the trench gate electrodes or of the trench Schottky electrode. The Schottky layer forms a Schottky contact to the collection area at a contact area.

Insulated gate bipolar transistor including trench Schottky electrode

A power semiconductor device comprises a semiconductor body, a gate electrode, and an extraction electrode, wherein the semiconductor body comprises a source region of a first conductivity type, well region of a second conductivity type different from the first conductivity type at the gate electrode, a drift region which is of the first conductivity type, and a barrier region which is of the first conductivity type, the barrier region is located between the drift region and the extraction electrode.

Power semiconductor device and manufacturiing method

A semiconductor device a first semiconductor layer of a first conductivity type at a first main side of a semiconductor wafer and a second semiconductor layer of a second conductivity type at second main side. The second semiconductor layer forms a pn junction with the first semiconductor layer. A first electrode is in ohmic contact with the first semiconductor layer and a second electrode layer is in ohmic contact with the second semiconductor layer. A first semiconductor region of the first conductivity type completely embedded in the second semiconductor layer and a second semiconductor region of the first conductivity type completely embedded in the second semiconductor layer.

Semiconductor device with gradual injection of charge carriers for softer reverse recovery

An insulated gate power semiconductor device (), comprises in an order from a first main side () towards a second main side () opposite to the first main side () a first conductivity type source layer (), a second conductivity type base layer (), a first conductivity type enhancement layer () and a first conductivity type drift layer (). The insulated gate power semiconductor device () further comprises two neighbouring trench gate electrodes () to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (). At least a portion of a second conductivity type protection layer () is arranged in an area between the two neighbouring trench gate electrodes (), wherein the protection layer () is separated from the gate insulating layer () by a first conductivity type channel layer () extending along the gate insulating layer ().

Insulated gate power semiconductor device and method for manufacturing such device

An insulated gate power semiconductor device includes an (n-) doped drift layer between an emitter side and a collector side. A p doped protection pillow covers a trench bottom of a trench gate electrode. An n doped enhancement layer having a maximum enhancement layer doping concentration in an enhancement layer depth separates the base layer from the drift layer. An n doped plasma enhancement layer having a maximum plasma enhancement layer doping concentration covers an edge region between the protection pillow and the trench gate electrode. The N doping concentration decreases from the maximum enhancement layer doping concentration towards the plasma enhancement layer and the N doping concentration decreases from the maximum plasma enhancement layer doping concentration towards the enhancement layer such that the N doping concentration has a local doping concentration minimum between the enhancement layer and the plasma enhancement layer.

Insulated gate power semiconductor device and method for manufacturing such a device

An insulated gate power semiconductor device has an (n&#x2212;) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench bottom and trench lateral sides and extends to a trench depth. A p doped first protection pillow covers the trench bottom. An n doped second protection pillow encircles the trench gate electrode at its trench lateral sides. The second protection pillow has a maximum doping concentration in a first depth, which is at least half the trench depth, wherein a doping concentration of the second protection pillow decreases towards the emitter side from the maximum doping concentration to a value of not more than half the maximum doping concentration. An n doped enhancement layer has a maximum doping concentration in a second depth, which is lower than the first depth, wherein the doping concentration has a local doping concentration minimum between the second depth and the first depth.

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Aarau, Switzerland

Luca De-Michielis