Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Ag

Infineon Technologies Ag

Luca De Ambroggi

Thomas Kern

Stefan Dietrich

Detlev Richter

Andreas Taeuber

Rainer Spielberg

Marco Redaelli

Giacomo Curatolo

Peter Schroegmeier

Konrad Seidel

Jens Christopher Egerer

Robert Petter

Marco Ziegelmayer

Francesco Maria Brani

An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.

Systems and methods for writing to a memory

A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.

Method for classifying memory cells in an integrated circuit

In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

Data bus width converter

A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.

Memories, method of storing data in memory and method of determining memory cell sector quality

A method adapts circuit components of a memory module to changing operating conditions within a predefined range. According to one embodiment, a memory module provides a sensor arrangement and a communication bus. Sub-ranges are defined for at least one operating condition, in which the circuit components can work with a fixed setup. During operation, the current state of the at least one operating condition is sensed using the sensing arrangement. The sensed state of the operating condition is mapped to one of the predefined ranges and an associated set of control signals is transmitted over the communication bus. The control signals transmitted over the communication bus are used to adapt at least one circuit component to the current operating conditions.

Method and apparatus for adapting circuit components of a memory module to changing operating conditions

A voltage generator circuit provides an output voltage that is higher than an input voltage. The voltage generator circuit includes an input terminal receiving the input voltage, and an output terminal providing the output voltage. A pre-charge element is coupled between the input terminal and the output terminal, and a capacitance circuit is coupled to the input terminal and to the output terminal.

Voltage generator circuit, method for providing an output voltage and electronic memory device

A semiconductor memory device comprises a wordline (), a first bitline (), two second bitlines (), a first memory cell () and a second memory cell (). The first memory cell () is coupled to the wordline (), one of the second bitlines () and the first bitline (). The second memory cell () is coupled to the wordline (), the other second bitline () and the first bitline (). Each memory cell () stores a first bit () and a second bit (). The semiconductor device further comprises a programming unit () coupled to the wordline () and the first and the second bitlines (). The programming unit () enables to apply a first programming potential (V) to the wordline () and to apply a third programming potential (V) to the second bitlines () while applying a second programming potential (V) to the first bitline () in order to program the first bit () of the second memory cell () and the second bit () of the first memory cell ().

Semiconductor memory device and method for writing data into the semiconductor memory device

A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased or a programmed state of a memory cell. In the circuitry area, additional main reference cells are provided, which are configured to also have a threshold voltage corresponding to an erased or programmed state of a memory cell. The main reference cells are used for setting of said array reference cells and said array reference cells are provided as a reference for reading or writing a state of said memory cells. A method is also provided for setting array reference cells in a non-volatile semiconductor memory device to a predefined threshold voltage.

Reference scheme for a non-volatile semiconductor memory device

A method of sensing a state of a non-volatile semiconductor memory cell is provided. A memory cell current as well as a comparative current generated from at least one reference cell are compared with a predefined reference current while the gate voltages of the cells are varied. Sense amplifiers detect which of said currents first reaches the predefined reference current. The order of reaching the reference current is indicative of the state of the memory cell. In a preferred embodiment of the invention the comparative current is generated as an average of an erased reference cell current and a programmed reference cell current.

Sensing scheme for a non-volatile semiconductor memory cell

Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit (B) and the second bit (B) coincide with their respective initial states and includes maintaining the initial states of the first bit (B) and the second bit (B). A second step is executed if both the first bit (B) and the second bit (B) have erased final states and the initial states of both the first bit (B) and the second bit (B) were not erased and includes erasing both the first bit (B) and the second bit (B). A third step is executed if neither the first bit (B) nor the second bit (B) is to be changed from a programmed initial state to an erased final state and includes programming the first bit (B) if the first bit (B) is to be changed from an erased initial state to a programmed final state, and/or programming the second bit (B) if the second bit (B) is to be changed from an erased initial state to a programmed final state. A fourth step is executed if only one of the first bit (B) and the second bit (B) is to be changed from a programmed initial state to an erased final state and includes first erasing both the first bit (B) and the second bit (B) and then programming the first bit (B) if the first bit (B) is programmed in the final state or programming the second bit (B) if the second bit (B) is programmed in the final state.

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Munich, Germany

Luca De Ambroggi