Other

Stmicroelectronics S.r.l.

Microsemi Storage Solutions (u.s.), Inc.

Micron Technology Incorporated

Pmc-sierra Us, Inc.

Hynix Semiconductor Inc.

Luca Crippa

Rino Micheloni

Giancarlo Ragone

Miriam Sangalli

Alessia Marelli

Roberto Ravasio

Giovanni Campardo

Peter Onufryk

Christopher I W Norrie

Ihab Jaser

Chiara Missiroli

Federico Pio

Salvatrice Scommegna

Angelo Bovino

Miram Sangalli

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

System and method for higher quality log likelihood ratios in LDPC decoding

A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

System and method for accumulating soft information in LDPC decoding

A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.

System and method for memory block pool wear leveling

A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells.

Nonvolatile memory system that uses programming time to reduce bit errors

Method of programming a multi-level memory cell may include transferring one or more values between an auxiliary latch of the multi-level memory cell and a most significant bit (MSB) latch of the multi-level memory cell and/or between the auxiliary latch and a least significant bit (LSB) latch of the multi-level memory cell while programming the multi-level memory cell.

Method of programming a multi-level memory device

A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and generates a corrected data unit by correcting data bit errors in the data unit based on the error correction code if the number of data bit errors in the data unit does not exceed an error correction capacity of the error correction code. Otherwise, the data storage device generates a modified data unit based on the data unit by negating at least one erroneous data bit the data unit based on the bit error indicator and corrects any remaining data bit errors in the modified data unit based on the error correction code.

Error correction code technique for improving read stress endurance

Methods and apparatus for programming a memory include programming cells to a first threshold voltage, verifying programming using a first verify voltage, and applying a test read voltage to verify again that the cells are programmed to the first threshold voltage. The test read voltage is lower than the first verify voltage.

A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

Circuit and method for retrieving data stored in semiconductor memory cells

A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.

Multistage regulator for charge-pump boosted voltage applications

A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.

Voltage regulator or non-volatile memories implemented with low-voltage transistors

The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Method of programming cells of a NAND memory device

A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N&#x3e;=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells.

Page buffer for multi-level NAND electrically-programmable semiconductor memories

Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by a plurality of comparators is connected to the high-voltage output and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output and a plurality of reference voltages, one for each comparator. The charge-pump stages are grouped into sets of stages, and the stages belonging to a same set receive a same enabling signal; thus, as many comparators as there are sets of stages are present.

Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile flash memories

A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations

A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.

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Busnago, Italy

Luca Crippa