Stmicroelectronics S.r.l.

Knowles Electronics, Inc.

Ams International Ag

Luca Bettini

Guido De Sandre

Mark Niederberger

Vezio Malandruccolo

Weiwen Dai

Gianni Giacomi

Adrian Ryser

A sensor assembly including a transducer and interface circuit with a DSL-controlled input voltage is disclosed. The interface circuit includes a logic circuit configured to generate and provide a pulse width and amplitude modulated (PWAM) signal to an n-bit iDAC coupled to an analog front end (AFE) amplifier or buffer. The PWAM signal is based on an output of a forward signal-path ADC or low-power ADC coupled to the AFE amplifier or buffer, wherein the n-bit iDAC regulates a voltage at the input of the AFE amplifier or buffer based on the PWAM signal.

Sensor assembly with interface circuit voltage control

The disclosure relates generally to microphone and vibration sensor assemblies () having a transducer (), like a microelectromechanical systems (MEMS) device, and an electrical circuit () disposed in a housing () configured for integration with a host device. The electrical circuit includes a transducer bias circuit that applies a bias to the transducer and a bias control circuit () that compensates for transducer sensitivity drift caused by variation in an environmental condition of the transducer, and electrical circuits therefor.

Microphone assembly with transducer sensitivity drift compensation and electrical circuit therefor

The disclosure relates generally to microphone and vibration sensor assemblies () having a transducer (), like a microelectromechanical systems (MEMS) device, and an electrical circuit () disposed in a housing () configured for integration with a host device. The electrical circuit includes a variable gain signal processing circuit () that processes an electrical signal from the transducer and a gain control circuit () that compensates for transducer sensitivity drift caused by variation in an environmental condition of the transducer, and electrical circuits therefor.

A charge pump circuit comprises a series circuit of a number N of stage circuits. A stage circuit comprises a converter circuit, a stage output, a stage input coupled via the converter circuit to the stage output, a first clock input and a second clock input coupled to the converter circuit, a control input and an activation transistor having a control terminal coupled to the control input and a first terminal coupled to the stage output.

Charge pump circuit and method for voltage conversion

An embodiment of a discharge circuit for evacuating electric charge accumulated in circuit nodes of a charge pump during a discharge phase consequent to a shutdown of the charge pump is proposed. The charge pump is configured to bias each circuit node with a corresponding pump voltage during an operational phase of the charge pump. The discharge circuit includes a generator circuit configured to generate a discharge current during the discharge phase. The discharge circuit further includes means for evacuating the electric charge stored in each circuit node of the charge pump during a corresponding portion of the discharge phase; such means for evacuating include a respective discharge stage for each circuit node of the charge pump. Each discharge stage includes a first discharge circuit branch and a second discharge circuit branch coupled to the corresponding circuit node. The discharge stage is configured to cause the discharge current flowing through the first discharge circuit branch&#x2014;during the portion of the discharge phase of the corresponding circuit node&#x2014;when the pump voltage of the corresponding circuit node is higher than a respective threshold, and through the second discharge circuit branch when the pump voltage of the corresponding circuit node is lower than said respective threshold.

Discharge circuit for voltage multipliers

An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device&#x2014;by a total delay. An embodiment of a corresponding method includes the steps of: preliminary programming the delay line to provide a selected nominal value of the total delay equal to a period of the timing signal, and trimming the delay line to vary an actual value of the total delay until the actual value of the total delay matches the period of the synchronization signal.

Trimming of a pseudo-closed loop programmable delay line

A device for programming PCM cells includes a pulse-generator circuit for supplying programming current pulses. The pulse-generator circuit includes: at least one first capacitive element; a charging circuit, connectable to the first capacitive element in a first operating condition, for bringing a reference voltage on the first capacitive element to a reset value; a discharge-current generator, selectively connectable to the first capacitive element in a second operating condition, for discharging the first capacitive element through a controlled discharge current; a logic unit, configured to control connection and disconnection of the first capacitive element), of the charging circuit, and of the discharge-current generator; and a voltage-to-current converter, for converting the reference voltage into current.

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Zurich, Switzerland

Luca Bettini