Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Luca Bertolini

Ezio Galbiati

Roberto Gariboldi

Domenico Rossi

Michele Berto Boscolo

Paola Galbiati

Giorgio Pedrazzini

Massimo Pozzoni

Michele Palmieri

Paolo Cordini

In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

Belowground and oversupply protection of junction isolated integrated circuits

A circuit for shifting the voltage level of a digital signal, comprising a first pair of transistors of a first polarity, which are connected to a high-voltage line, and a second pair of transistors of a second polarity, which are connected to a ground line; the first and second pairs of transistors are connected to each other by means of the drain terminals of the respective transistors; an input voltage is applied to the gate terminals of the first pair of transistors. The circuit further includes a secondary circuit for leveling the gate voltages of the transistors of the first and second pairs, which is connected between the first and second pairs of transistors and whereto at least one reference voltage is applied. The circuit also includes an output stage, whose output is a voltage which is shifted in level with respect to the input voltage. The secondary circuit limits the gate-source voltage value of the first pair of transistors to a value which is independent of the voltage value of the high-voltage line, so as to prevent damage to the first pair of transistors.

Circuit for shifting the voltage level of a digital signal

A current sensing circuit with high input impedance comprises a first transconductance amplifier connected across the terminals of a resistor, through which a current to be measured flows. A voltage amplifier is cascade-connected to the first transconductance amplifier. A second transconductance amplifier is feedback connected between an output of the voltage amplifier and a virtual ground node of the voltage amplifier. A ratio between the output voltage of the voltage amplifier and the voltage across the resistor are equal, in absolute value, to a ratio of the transconductances of the first and second transconductance amplifiers.

Current sensing circuit with high input impedance

The control of the current in a PWM mode through independently controlled windings of a multi-phase motor driven in a 'bipolar' mode is implemented by employing only two sense resistors and related control loops. This is so regardless of the actual number of windings of the motor.

Current control in driving DC-brushless motor with independent windings

A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Power output stage with limited current absorption during high-impedance

A regulator including a power element between the input terminal and output terminal; and a regulating loop including a differential stage for comparing the output voltage of the regulator with a reference voltage and accordingly driving a gain stage connected to the power element. The output voltage is picked up by the differential stage via a resistive divider, the resistance of which varies according to the value of a logic signal at a control input. When the resistance of the divider changes, the inputs of the differential stage are so unbalanced as to produce an output voltage up or down ramp equal to the slew rate of the regulating loop and proportional to the bias current of the differential stage. Over the up ramp, the shorting protection circuit is turned off for a predetermined time .tau., whereas, over the down ramp, a stage is turned on for absorbing the discharge current of the capacitive load.

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Milan, Italy

Luca Bertolini