Arteris, Inc.

Qualcomm Incorporated

Qualcomm Technologies, Inc.

Luc Montperrus

Philippe Boucard

Jean-Jacques Lecler

Rakesh Kumar Gupta

Christophe Layer

Christophe Avoinne

Pascal Godet

Data may be communicated from a sender device to a receiver device over enabled or selected byte positions or other data bit groups of a data bus. The sender device may determine data values to be sent over the data bus and may determine which byte positions are enabled or selected and which are not selected. The sender device may also determine a code. The code may be a value that is not included in the data values to be sent over the data bus. The sender device may then send the selected data values in selected byte positions of the data bus and send the code in non-selected byte positions of the data bus. The sender device may also send the code to the receiver device separately from the data bit lanes of the data bus.

Encoding byte information on a data bus with separate code

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Coherent interconnect power reduction using hardware controlled split snoop directories

An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside.

Electronic memory device

The message switching system () comprises at least two inputs () and at least one output (), first arbitration means () dedicated to said output (), and management means () designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system () and having sent requests for the assignment of said output (), and designed to assign said output (). Said management means () comprise storage means () designed to store said relative orders OR(i,j), initialization means () designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means () designed to update all of said relative orders when a new request arrives at said first arbitration means (), or when said output is assigned to one of said inputs.

Message switching system

Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.

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Montigny le Bretonneux, France

Luc Montperrus