Imec

Imec Vzw

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Interuniversitair Micro-elektronica Centrum Vzw

Infineon Ag

Other

Katholieke Universiteit Leuven, Ku Leuven R&d

Interuniversitair Microelektronica Centrum (imec)

Luc Haspeslagh

Andy Lambrechts

Jan F Van Houdt

Nicolaas Tack

Guido V Groeseneken

Herman E Maes

Ludo Deferm

Ann Witvrouw

Philippe Soussan

Constantine N Anagnostopoulos

Xavier Rottenberg

Simone Severi

Veronique Rochus

Bernardette Kunert

Deniz Sabuncuoglu Tezcan

Robert Langer

Klaas Tack

Yunlong Li

Gert Claes

Vasyl Motsnyi

Gauri Karve

Stefano Guerrieri

Olga Syshchyk

Bin Guo

Agnes Verbist

Piet De Moor

Atze De Vries

Brigitte Parmentier

According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed. The method results in a hybrid wafer comprising a planar top layer formed of the material of the continuous layer with one or more islands embedded therein, the top layer of the islands being formed by the top layer of the active material portion of the one or more tiles.

Method of producing hybrid semiconductor wafer

A method for calibrating an image sensor begins by illuminating a portion of the image sensor with an input light spectrum, where the input light spectrum includes light of known wavelength and intensity. The method continues by sampling an output for each optical sensor of the image sensor, where each optical sensor is associated with one or more optical filters and where each optical filter being associated with a group of optical filters of a plurality of groups of optical filters. Each optical filter of a group of optical filters is configured to pass light in a different wavelength range and at least some optical filters in different groups of the plurality of groups of optical filters are configured to pass light in substantially a same wavelength range. The method then continues by comparing a sampled output for each optical sensor of the plurality of optical sensors with an expected output and generating a calibration factor for each of at least a subset of the plurality of optical sensors and storing the generated calibration factors in memory.

Hyperspectral image sensor with calibration

The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.

Method of forming a semiconductor device structure

An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non-monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.

Integrated circuit for spectral imaging system

An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors.

A DND device is disclosed. In one aspect, the device includes a nano-mirror (), and an actuating module configured to move the nano-mirror in an upward and/or downward position. The actuating module has a cantilever mounted to a fixed structure, and at least one first electrode for moving the cantilever in an upward and/or downward position. Such DND devices may be arranged in a 2D array.

Diffractive optical nano-electro-mechanical device with reduced driving voltage

A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Method of manufacturing a semiconductor device and semiconductor devices resulting therefrom

The present invention relates to a method of making a multibit non-volatile memory and especially to a method of making a flash memory such as a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on hot-electron injection for programming which is particularly suited for high density low-voltage low-power applications and employs only two polysilicon layers.

Method of making a multibit non-volatile memory

A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.

Multibit non-volatile memory and method

The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.

Method for producing micromachined devices and devices obtained thereof

A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.

Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure

The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.

Growing community of inventors

Linden, Belgium

Luc Haspeslagh