International Business Machines Corporation

Globalfoundries Inc.

Other

Luc Gilbert Guerin

Jean Audet

Sylvain E Ouimet

Van Thanh Truong

Bing Dang

Richard D Langlois

Steve E Whitehead

Mario John Interrante

Chirag Suryakant Patel

Stephan L Martel

Jean-Luc Landreville

Gerald P Audet

Paul Stephen Andry

Peter Alfred Gruber

Russell Alan Budd

David John Russell

Benjamin V Fasano

David L Questad

Michael Jay Shapiro

Paul Francis Fortier

David Hirsch Danovitch

Christian Bergeron

Thuy L Tran-Quinn

Maxime Cadotte

David Clifford Long

Charles Leon Arvin

Thomas Weiss

Frank Robert Libsch

Jon Alfred Casey

Mark J LaPlante

Thomas Anthony Wassick

Patrick Anthony Coico

Glenn A Pomerantz

Marc Douglas Knox

Sylvain Pharand

Gregory Blair Martin

Thomas P Moyer

Maryse Cournoyer

Pascale Gagnon

Robert G Haas

Clement J Fortin

Pascal P Blais

Eric Bouchard

George J Lawson

Francois Arguin

Nathalie Meunier

Frank F Libsch

Chrirag S Patel

The present invention provides a wind deflector adapted for use with a truck pulling a trailer in conventional towing arrangement, with a towing hitch attached to the rear of the truck. The wind deflector has a panel that extends at an angle behind the rear end of the truck, such that the deflector panel acts as a wind deflecting surface that reduces the gap between the truck and the trailer and improves aerodynamic drag. The invention also provides an inclinable truck bed tailgate that can support the deflector. Tailgate can also be adapted for storing the deflector when not in wind deflecting position, and to extend the deflector for towing. The deflector can comprise multiple panel portions that can be folded together. The deflector brings fuel economy in the order of 18% with the truck and trailer vehicle combination, thereby lowering the environmentally harmful emissions.

Wind deflector for a vehicle towing a trailer

A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.

High-density chip-to-chip interconnection with silicon bridge

A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.

Flip chip assembly with connected component

A system for laser ashing of polyimide for a semiconductor manufacturing process is provided. The system includes: a semiconductor chip, a top chip attached to the semiconductor chip by a connection layer, a supporting material, a polyimide glue layer disposed between the supporting material and semiconductor chip, a plasma asher, and an ashing laser configured to ash the polyimide glue on the semiconductor chip.

Laser ashing of polyimide for semiconductor manufacturing

A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.

All intermetallic compound with stand off feature and method to make

An assembly including a liquid thermal interface material for surface tension adhesion and thermal control used during electrical/thermal test of a 3D wafer and methods of use. The method includes temporarily attaching a thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the thinned wafer and the blank silicon-based carrier wafer together.

Temporary liquid thermal interface material for surface tension adhesion and thermal control

A method for laser ashing of polyimide for a semiconductor manufacturing process using a structure, the structure comprising a supporting material attached to a semiconductor chip by a polyimide glue, includes releasing the supporting material from the polyimide glue, such that the polyimide glue remains on the semiconductor chip; and ashing the polyimide glue on the semiconductor chip using an ablating laser.

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Solder ball contact susceptible to lower stress

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Silicon carrier optoelectronic packaging

A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.

Technique for verifying the microstructure of lead-free interconnects in semiconductor assemblies

Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

Techniques for forming solder bump interconnects

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CA

Luc Gilbert Guerin