Jds Uniphase Corporation

Alcatel Lucent

Viavi Solutions Inc.

Alcatel-lucent Canada Inc.

Luc Chouinard

David George Coomber

Emmanuelle Marie Josèphe Janz

Kizito Gysbertus Antonius Van Asten

Patrick Gene Russell

Richard Charles Vieregge

A programmable transceiver for a network element includes a programmable circuit including internal logic and control logic. Interfaces connect the programmable circuit to a network and a network element. The control logic facilitates programming of the internal logic responsive to an in-band program signal while the programmable circuit services network traffic received via at least one of the interfaces.

Upgrading a programmable logic gate array in an in-service pluggable transceiver

Devices and methods for partially upgrading a programmable pluggable transceiver that is in service using the regular datapaths without degrading the basic transparent, hitless pass-through functionality of the transceiver. The programmable logic gate array can be divided into four generalized parts: core logic for basic transceiver pass-through functionality over the datapaths, upgradeable internal logic, connectivity logic for selectively outputting on the datapaths from the core and internal logics, and control logic for isolating, upgrading and reconnecting the internal logic without affecting the basic transparent hitless pass-through functionality of the transceiver.

A pluggable transceiver, and its use, looping back Layer 2 and higher data in an Ethernet network element. The transceiver has upstream and downstream datapaths, a logic array having first and second complimentary latching loopback logic blocks (LLBLBs) connected in series through both datapaths. The first LLBLB receiving an upstream datapath frame, comparing it to loopback conditions and looping back the frame on the downstream datapath if the conditions match. If the conditions did not match, the frame is sent to the other LLBLB. The first LLBLB receiving a frame from the second LLB and transmitting it on the upstream datapath with priority over any loop back frames to maintain the upstream throughput requirements of the pluggable transceiver. The second LLBLB operates in mirror image with respect to the datapaths.

Layer 2 and 3 latching loopbacks on a pluggable transceiver

An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

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Ottawa, Canada

Luc Chouinard