Em Microelectronic-marin Sa

Lubomir Plavec

Filippo Marinelli

Yves Theoduloz

Hugo Jaeggi

Christoph Kuratli

Mario Dellea

Petr Drechsler

Mathieu Coustans

Michal Prazan

Zdenek Lukes

Miloslav Kubar

Yves Théoduloz

Ondrej Subrt

A soft switching device (sw) for connecting a power supply to at least one large electronic unit of an electronic system (), so as to be activated via the soft switching device to the power supply. The device comprises a switch component (M) with a control terminal and a current source () connected to the control terminal to control the switch component closure when the current source is activated. The soft switching device also includes a soft transition element (C) of capacitive type between the output terminal () and the control terminal of the switch component (M) so as to gradually close the switch for connection to a power supply.

Soft switching device, electronic system with soft switching device with an electrical power source

The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK) and an output (S), a first capacitor (C) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.

Elementary cell and charge pumps comprising such an elementary cell

The integrated circuit connection device () enables an external component to be connected. The integrated circuit is powered by a supply voltage (V) and part of the circuit operates using at least one internal regulated voltage (V). The connection device includes two active transistors (N, P) of different conductivity connected in series between the supply voltage (V) and earth (V). The drains of these two active transistors (N, P) are connected to each other so as to form an external contact pad (). The gates of these active transistors are controlled by voltage signals that have the same amplitude (V). The connection device further includes switching means () for modifying the control signals (V) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (V) and the internal regulated voltage (V). This allows the voltage range of said integrated circuit to be adapted to an external component connected to the external contact pad ().

Integrated circuit connection device

The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises

Regulation circuit for a charge pump and method of regulation

The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Electronic memory device and test method of such a device

A memory circuit is provided, including at least one bit cell configured to store data and having a first terminal and a second terminal, one of the terminals being coupled to a bit-line; at least one current switch connected to the bit-line and connected to a current source and being configured to selectively provide at least a read current to the bit cell; and a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is disposed between the bit cell and the at least one current switch.

Memory circuit including a current switch and a sense amplifier

A fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly includes a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes includes a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.

Fault detection assembly

The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Variable pulse width signal generator

The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Voltage regulator

The integrated circuit device () backs up the configuration of output terminals (O, S) of said integrated circuit in low-power mode. To do this, the device includes several voltage level shift units ('&#x2033;) and an output stage () connected to each output of the level shift units and connected to at least one external contact pad (S) of said integrated circuit. Each level shift unit includes an input stage powered by a regulated internal voltage (V) and a part for transferring the state of a specific output function, which is powered by a supply voltage (V) of the integrated circuit. Each level shift unit also includes a memory cell at output powered by the supply voltage, for storing the output state of a specific function of the level shift unit in the idle mode of the integrated circuit where the regulated voltage is cut off.

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Brno, Czechia

Lubomir Plavec