Rca Inc.

General Electric Company

Harris Corporation

Lubomir L Jastrzebski

John F Corboy, Jr

Scott C Blackstone

Robert H Pagliaro, Jr

Alfred C Ipri

Jacek Lagowski

Peter Alan Levine

Joseph Thomas McGinn

Ramazan Soydan

Guenther Harbeke

Donald J Sauer

Gary W Looney

Achilles G Kokkas

Ronald J Johansson

David L Patterson

A method for forming dielectrically isolated devices comprises forming a first insulating layer on a flat monocrystalline surface of a silicon wafer. A plurality of active regions is defined on the surface using existing manufacturing masks. Portions of the insulating layer not included in the device regions are removed, leaving apertures. Silicon is epitaxially deposited within the apertures and over the first insulating layer so as to form a continuous monocrystalline layer. The surface of the monocrystalline is oxidized. The resulting oxide is then removed, thereby exposing the surface of the monocrystalline layer having its thickness reduced. A second insulating layer is formed over the monocrystalline layer, and a layer of silicon nitride is deposited over the second insulating layer. The plurality of active regions is defined on the layer of silicon nitride, again using existing manufacturing masks. Portions of the silicon nitride layer and the second insulating layer not included within the active regions are removed. Portions of the monocrystalline silicon layer thus exposed are oxidized to form oxide-isolated island portions of the monocrystalline silicon layer. The remaining portions of the silicon nitride and the second insulating layer are removed and devices are formed in the island portions.

Method for forming dielectrically isolated transistor

A mask of insulating material is formed on the major surface of a semiconductor wafer, the mask including apertures to the wafer surface. A layer of monocrystalline silicon is then formed through the apertures and over the mask. The silicon within each aperture is next replaced with an insulating plug and epitaxial silicon is grown from the remaining portions of the monocrystalline silicon layer so as to form a continuous monocrystalline silicon sheet overlying the mask and plug.

Method for making a silicon-on-insulator substrate

The present invention provides a method of treating a SIMOX wafer so that oxygen precipitates and heavy metal, carbon, and other contaminants are substantially reduced. The method includes forming a protective layer on the SIMOX surface, heating the wafer and protective layer so that the precipitates and contaminants disolve and diffuse into the protective layer, and slowly cooling the wafer to permit continued diffusion during cooling.

High temperature annealing to improve SIMOX characteristics

The present invention provides graphs and a method of using the graphs to determine the substrate temperature used during oxygen implantation of SIMOX wafers. The method establishes a relationship between the wavelength of minimum transmittance for infrared energy and the implantation temperature. Such relationships are then expressed, in the form of graphs, for various selected oxygen dose and energy levels.

Determination of substrate temperature used during oxygen implantation

The present invention is a method of making an integrated circuit device including a pair of MOSFETs each of which has a source or drain region which shares a common active region with the other. The method includes forming an epitaxial layer from nucleation sites, one of which is the source or drain region of the first MOSFET. The second MOSFET is then formed in the epitaxial layer so that one of the source or drain regions extends from one of the nucleation sites.

Method of making integrated circuit with pair of MOS field effect

The present invention provides an optical method of quickly, easily, and accurately determining the degree of amorphism, surface roughness, and presence of a contaminating film on the surface of a SIMOX article. The reflectances of the SIMOX material and a reference single crystalline silicon material are compared. Reflectances are obtained at three selected wavelengths and used to evaluate three simultaneous equations which yield values for the parameters A, B, and C when A, B, and C represent the degree of amorphism, surface roughness, and surface contamination respectively.

Optical reflectance method of examining a SIMOX article

A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a silicon

A plurality of first cavities is formed in the planar surface of a silicon substrate. A first oxide region of predetermined thickness is formed in each of the first cavities such that each of the first oxide regions has a surface which is coplanar with the substrate surface. A layer of monocrystalline silicon is then epitaxially deposited over the planar first oxide region/substrate surface. Second cavities are then formed through the monocrystalline silicon layer and into the substrate adjacent the first oxide regions, extending to a depth equal to approximately one-half that of the first oxide regions. The second cavities are then thermally oxidized so as to form second oxide regions therein, these second oxide regions being coplanar with the first oxide regions. Silicon is next epitaxially deposited on those portions of the monocrystalline silicon layer remaining on the first oxide regions so as to yield a continuous monocrystalline silicon sheet over the first and second oxide regions.

Recessed oxide method for making a silicon-on-insulator substrate

A method for depositing monocrystalline silicon at a uniform rate onto a plurality of unequally sized monocrystalline nucleation sites comprises initially providing a substrate having an apertured oxide mask on a major surface thereof. The oxide mask includes a plurality of apertures each of which exposes a nucleation site on the substrate surface. The substrate is then exposed to a mixture of dichlorosilane and hydrogen chloride at 850.degree. C. and a pressure less than approximately 50 torr, for a predetermined time. This yields a monocrystalline silicon island extending from each nucleation site. Each of the islands has a substantially flat profile across the major surface thereof and all islands are equal in thickness.

Method of depositing uniformly thick selective epitaxial silicon

Method for forming dielectrically isolated PMOS, NMOS, PNP and NPN

The yield of field transfer CCD imagers made in a wafer of single crystalline silicon is improved by making the imagers in groups of at least two imagers, and preferably four imagers, with the A-registers of all the imagers in a group being adjacent each other. The groups of imagers are formed in columns on the surface of the wafer with one group being at the center of the wafer and the other group being around the center group and positioned radially outwardly form the center group toward the edge of the wafer.

Arrangement of semiconductor devices on a wafer

Crystalline quality of a semiconductor material near its interface with an insulator is evaluated by the photovoltage response to a light beam scanned in wavelength. The crystalline quality is determined from the photovoltage interference pattern in the region of intrinsic excitation of the material. A body of silicon-on-sapphire (SOS) is used to illustrate the method.

Method to determine the crystalline properties of an interface of two

A method for forming a CMOS FET structure includes the steps of forming an apertured insulating layer on a silicon substrate and epitaxially forming a monocrystalline silicon island of first conductivity type through an aperture therein. The exposed surface of the silicon island is then thermally oxidized and the portion of the insulating layer not covered by the oxide is removed. A monocrystalline silicon island of second conductivity type is then formed adjacent to the oxidized silicon island of first conductivity type.

Fabricating of a CMOS FET with reduced latchup susceptibility

A method for substantially uniformly thinning a silicon layer comprises providing a silicon layer having a surface, oxidizing substantially all of the surface so as to transform a uniformly thick layer of silicon into oxide, and removing all the oxide so as to expose the silicon layer.

Method for thinning silicon

Monocrystalline silicon is deposited on first and second portions of a substrate, the first and second portions having substantially unequal dimensions. The method comprises subjecting the substrate to a silicon-source gas and a predetermined concentration of chloride at a predetermined temperature. The chloride concentration is selected so as to create a substantially equally thick monocrystalline silicon deposit on each of the substrate portions.

Growing community of inventors

Plainsboro, NJ, United States of America

Lubomir L Jastrzebski