Texas Instruments Corporation

Luat Q Pham

Francisco A Cano

Graham S Tubbs

Joe F Sexton

Sridhar Vajapey

Daniel L Essig

An output buffer 10 of an integrated circuit controls the slew rate of an output signal in order to minimize electro-magnetic interference. Transient current delay circuits 132 and 134 provide a delay between turning off pull down circuit 122 and turning on pull up circuit 124, and vice versa, in order to assure that driver overlap does not occur. Pull up circuit 124 selectively switches a plurality of output transistors P(n) in order to control the rise time of an output signal. Likewise, pull down circuit 122 selectively switches a plurality of output transistors N(n) in order to control the fall time of an output signal so that current spikes on supply lines to output buffer 10 are reduced or eliminated.

CMOS output buffer with slew rate control

A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first voltage level. Other bit lines (22) are maintained at a second voltage level. After data has been read from the memory (10), the first group of bit lines (22) is discharged to the second voltage level.

Method and apparatus for reducing failures due to bit line coupling and

A method and apparatus are disclosed for self-timing the precharge of bit lines (22) in a memory array. A reference column bit line (26) is charged to create a reference column voltage. The bit lines (22) in the memory array (12) are precharged until the reference voltage exceeds a first threshold.

Method and apparatus for self-timed precharge of bit lines in a memory

A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.

Growing community of inventors

Houston, TX, United States of America

Luat Q Pham