Micron Technology Incorporated

Round Rock Research, LLC

Other

Intel Corporation

Luan C Tran

Tyler A Lowrey

D Mark Durcan

John K Lee

Gurtej S Sandhu

Gordon A Haller

Mirzafer K Abatchev

Yushi Hu

Robert B Kerr

William T Rericha

Hongbin Zhu

Alan R Reinberg

John David Hopkins

Ravi T Iyer

Fred D Fishburn

Leonard Forbes

Kie Y Ahn

Chandra V Mouli

Pai-Hung Pan

Eric Higgins Freeman

Ramakanth Alapati

Russell Nielsen

Howard E Rhodes

Zhiping Yin

Paul A Morgan

Shuang Meng

Puneet Sharma

Sheron Honarkhah

Kunal Shrotri

Jingyi Bai

Mark D Durcan

Jie Li

Mark A McQueen

Yongjun Jeff Hu

Rita J Klein

Hongmei Wang

Ardavan Niroomand

Brent D Gilgen

Zengtao “Tony” Liu

Bill Stanton

John Mark Meldrim

Howard Kirsch

Minsoo Lee

Charles L Turner

James Mathew

David F Cheffings

Raghupathy Giridhar

Yangda Zhang

Hongpeng Yu

Fernando N Gonzalez

Kirk D Prall

Haitao Liu

Arup Bhattacharyya

Paul A Farrar

Krishna Kumar Parat

Fatma Arzum Simsek-Ege

Joseph E Geusic

Eugene H Cloud

Shubneesh Batra

Brian M Shirley

Zengtao T Liu

Stephen R Porter

Kris K Brown

Guangyu Huang

Richard D Holscher

Brett W Busch

Scot M Graham

Steven Howell

Meng-Wei Kuo

D Mark Duncan

Rob B Kerr

David H Wells

Ulrich C Boettiger

Zhiqiang (Jeff) Wu

Anish A Khandekar

Rongsheng Yang

Lijing Gou

Yoshiki Hishiro

Richard L Stocks

David J McElroy

Hyuntae Kim

Kevin G Donohoe

Fernando Gonz&aacute;lez

Raman Alapati

Jingyi (Jenny) Bai

John M Meldrin

David J Mcelroy

Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Methods of forming electronic devices using pitch reduction

The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

Memory having a continuous channel

A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

Memory array and methods used in forming a memory array

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Memory cell pillar including source junction plug

Methods for device fabrication using pitch reduction

Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Integrated structures and methods of forming integrated structures

Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

Replacement control gate methods and apparatuses

A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

Transistors and arrays of elevationally-extending strings of memory cells

Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Methods of fabricating integrated structures

Memory arrays and methods of fabricating integrated structure

Growing community of inventors

Meridian, ID, United States of America

Luan C Tran