Cisco Technology, Inc.

Altera Corporation

Luan Bui

Subramani Ganesh

Sreedhar Ravipalli

Raghucharan Boddupalli

Jing Miao

Dinesh Kotti

Murali Chundi

Ranjini Rajeevan

Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.

Chained command architecture for packet processing

First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit. Next, the packet may be sent to a first in first out (FIFO) memory. The packet may then be sent from the FIFO memory out the port exit.

Timestamp estimation and jitter correction using downstream FIFO occupancy

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San Jose, CA, United States of America

Luan Bui