International Business Machines Corporation

Luai A Abou-Emara

Ronald Nick Kalla

Jen-Yeu Chen

Mark David McLaughlin

Jorge N Yanez

A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Programming in a simultaneous multi-threaded processor environment

Programming in a simultaneous multi-threaded processor environment including permitting apparently exclusive access to multiple threads and disabling processor features during thread testing

A system includes a 'found two' module configured to receive an n-bit vector and to generate a 'found two' signal indicating whether there are at least two bits of the n-bit vector in a predetermined state. The system also includes a &#x201c;one's hot&#x201d; module coupled to the &#x201c;found two&#x201d; module. The &#x201c;one's hot&#x201d; module is configured to generate, concurrently with the &#x201c;found two&#x201d; module, a first one's hot vector (OHV) based on the received n-bit vector. In one embodiment, the system and method indicate whether an input n-bit vector contains at least two high bits.

System and method for improved vector analysis

A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.

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Austin, TX, United States of America

Luai A Abou-Emara