Texas Instruments Corporation

Qualcomm Incorporated

Lu Yuan

Hugo Cheung

Terence Chiu

Sharad Deepak Sambhwani

Danlu Zhang

Mehraban Iraninejad

Ramesh Saripalli

Peter S Gaal

Tingfang Ji

Wei Zeng

Muhammad Sayed Khairy Abdelghaffar

Renqiu Wang

Avneesh Agrawal

Mehmet Yavuz

Aziz Gholmieh

Arjun Bharadwaj

Charles E Wheatley, Iii

Joseph Patrick Burke

Bibhu P Mohanty

Pavan Kumar Vitthaladevuni

Saeid Sahraei

Yibo Jiang

Bolanle Oladapo Onodipe

Bibhu Prasad Mohanty

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a network entity may receive a sounding reference signal (SRS) at a multi-panel system of the network entity, where the multi-panel system includes one or more sounded panels and one or more non-sounded panels. The network entity may estimate a channel to obtain channel state information (CSI) for the one or more sounded panels based at least in part on the SRS. The network entity may estimate CSI for the one or more non-sounded panels based at least in part on the CSI for the one or more sounded panels. The network entity may transmit or receive a communication based at least in part on the CSI for the one or more sounded panels and the CSI for the one or more non-sounded panels. Numerous other aspects are described.

Estimation of channel state information for non-sounded panels or subpanels based on sounded panels or subpanels

Techniques for reporting acknowledgement (ACK) information and channel quality indication (CQI) information in a wireless communication system are described. A user equipment (UE) may be able to receive data from up to two cells with dual-cell operation. The UE may determine CQI information for a first cell, determine CQI information for a second cell, and send the CQI information for both cells on a feedback channel with a single channelization code. The UE may process a control channel from each cell and, if control information is received from the cell, may further process a data channel from the cell to receive data sent to the UE. The UE may determine ACK information for each cell based on processing results for the data and control channels from that cell. The UE may send the ACK information for both cells on the feedback channel with the single channelization code.

Reporting of ACK and CQI information in a wireless communication system

Techniques for estimating thermal noise and rise-over-thermal (RoT) in a communication system are described. Thermal noise in a sideband may be measured and used as an estimate of thermal noise in a signal band. In one design, samples containing a desired signal centered at DC or a frequency higher than DC may be partitioned into blocks of K samples. Each block of K samples may be transformed with an FFT to obtain a corresponding block of K transform coefficients for K frequency bins. The power of transform coefficients for frequency bins in the sideband may be computed. Thermal noise may be estimated based on power values for the frequency bins in the sideband. Power values for frequency bins in the signal band may also be obtained and used to estimate total received power. RoT may then be estimated based on the estimated thermal noise and the estimated total received power.

FFT-based estimation of thermal noise and rise over thermal in a wireless communication system

Techniques for estimating thermal noise and rise-over-thermal (RoT) in a communication system are described. In an aspect, thermal noise in a sideband may be measured and used to estimate thermal noise in a signal band. In one design, received power in the sideband may be measured, e.g., by computing total power of FFT transform coefficients within the sideband. Thermal noise may be estimated based on (e.g., by filtering) the measured received power in the sideband. Received power in the signal band may also be measured. Total received power may be estimated based on (e.g., by filtering) the measured received power in the signal band. RoT may then be estimated based on the estimated thermal noise and the estimated total received power. The estimated RoT may be used to estimate an available load for a cell, which may be used to admit and/or schedule users in the cell.

Estimation of thermal noise and rise-over-thermal in a wireless communication system

There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.

Method and system for providing security to processors

An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Method and device for providing high data rate for a serial peripheral interface

A method and apparatus is provided for that includes an improved special function register (SFR) access scheme by using a clock tree distribution process. In accordance with an exemplary embodiment, a conditional SFR write strobe signal may be used to trigger the SFR registers. A clock tree distribution process may be used to achieve significantly higher system speed. When balancing the clock network of the system, the clock leaf of the flip-flop or other circuit element that generates the SFR write strobe signal may be 'advanced' by connecting the circuit element directly to the clock root. In addition, the SFR write strobe signal distribution may be balanced as a separate clock tree with minimum insertion delay.

System and method for providing a write strobe signal to a receiving element before both an address and data signal

An external interface for a microprocessor system uses a programmed configuration bit to establish the functionality of a computer port, which improves external interface data transfer speed and input/output power consumption. In particular, the configuration bit allows the microprocessor user to establish the computer port as a memory port, input/output port or the like. The configuration bit is provided to the computer port at system power up or reset. Moreover, the configuration bit may be stored in flash memory and provided to the microprocessor computer port or, in the alternative, the configuration bit may be provided to the computer port directly via the microprocessor bus interface.

Method and device for providing and external interface using a programmed configuration bit in flash memory

The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a bus interface connected to one or more peripheral interface using logic processes to enable microcontroller-based products and other components and devices to achieve a low power data transmission between central processors and peripheral devices. In accordance with an exemplary embodiment, a low power embedded system bus architecture comprises logic devices, for example, an OR gate for passing through only data from a selected peripheral device. To facilitate the throughput of data, the non-selected peripheral devices may only provide logic zero to the OR gate. The logic device arrangement may comprise any combination of logic devices which performs the function of eliminating the need for tristate buffers. Through the elimination of tristate buffers, the present invention can lower the power consumed by the microcontroller, and improves the ability to test a large portion of the devices. In accordance with an exemplary embodiment, an AND gate is provided in each peripheral device for providing a logic zero when the peripheral device is not selected, and for providing data when the peripheral device is selected. In addition the AND gate eliminates the occurrence of high impedance Z states.

Method and device for providing a low power embedded system bus architecture

An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware. In addition, once an SPI transmit/receive request is made, data communication can be established between the transmit/receive buffer and the memory. To avoid structural hazard, the transmit/receive request can be suitably pipelined until the next available clock phase, for example, within one instruction cycle. As a result, for a 4 Mhz clock rate, the technique can enable a significantly higher data transfer rate, e.g., at 250 Kbytes per second, an improvement of almost twenty times the prior art data rates. The high performance technique also avoids the firmware overhead with minimum hardware control cost. For example, compared to the hardware approach using deeper buffer structures, e.g., with FIFO buffers implemented using flip-flop devices, the exemplary techniques utilize memory, e.g., dynamic or static random access memory (DRAM or SRAM) with direct memory access (DMA).

A method and apparatus is provided for performing an intelligent power-on-reset, and enabling the verification of a current voltage level with a reconfigurable brown out reset voltage level. In addition, the verification process may be selectively bypassed. Furthermore, the flash memory provides storage for the reconfigurable brown out reset voltage level and selected verification process enable/disable signal. In addition, the verification process occurs in a second phase during which some devices are released from reset mode and then those devices control the verification process.

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Carlsbad, CA, United States of America

Lu Yuan