Synopsys, Inc.

Cadence Design Systems, Inc.

Lu Sha

Ross Alexander Donelly

William C Naylor

Jonathan Frankle

Krishna Prasad Belkhale

Hussein Etawil

Disclosed are methods and systems for formulating a wirelength estimate that takes into account whether any of the routing directions are unavailable. Under certain circumstances, one or more of the routing layers may not be available for routing a wire. If this occurs, then the bounding box that is determined for performing the wirelength estimate would take into account the unavailability of the layer.

Method and system for implementing an analytical wirelength formulation for unavailability of routing directions

A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement. Other component functions are wire-length, which measures total linear wire-length, delay, which measures circuit timing, and power, which measures circuit power consumption. The barrier metric penalizes placements with cells outside the allowed placement region. A conjugate-gradient process utilizes both the MOF and its gradient to determine a next cell placement. The gradient is the vector of partial derivatives of the MOF with respect to all variables. The non-linear optimization process calls the MOF and gradient function subroutines and uses the results to minimize the MOF.

Non-linear optimization system and method for wire length and delay optimization for an automatic electronic circuit placer

A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well, spread out the cells are in the placement. Other component functions are wire-length, which measures total linear wire-length, delay, which measures circuit timing, and power, which measures circuit power consumption. The barrier metric penalizes placements with cells outside the allowed placement region. A conjugate-gradient process utilizes both the MOF and its gradient to determine a next cell placement. The gradient is the vector of partial derivatives of the MOF with respect to all variables. The non-linear optimization process calls the MOF and gradient function subroutines and uses the results to minimize the MOF.

Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer

Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer

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San Jose, CA, United States of America

Lu Sha