Intel Corporation

Lu Liu

Sanjay Rangan

Kiran Pangal

Nevil N Gajera

Koushik Banerjee

Gayathri Rao Subbu

Innocenzo Tortorelli

Hongmei Wang

Mattia Boniardi

Enrico Varesi

Hemant P Rao

Phoebe P Yeoh

A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application of a current pulse amplitude profile to the memory cell, wherein the current pulse amplitude profile decreases progressively, encompassing at least four different current pulse amplitudes, the at least four different current pulse amplitudes including a highest current pulse amplitude and a lowest current pulse amplitude.

Apparatus, method and system to reduce memory window latency and read disturb in a memory device for memory operations

One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

Set technique for phase change memory

Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

Tailoring current magnitude and duration during a programming pulse for a memory device

Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Multistage set procedure for phase change memory

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Boise, ID, United States of America

Lu Liu