Motorola Corporation

Tii Industries, Inc.

Lowell E Clark

Robert Bruce Davies

Israel A Lesk

Raymond Mervin Roop

David F Mietus

Bernard W Boland

Robert E Rutter

Vern H Winchell, Ii

David N Okada

James R Washburn

Thomas A Scharr

Charles E Volk

Jack L Saltich

A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.

Backside processing method

A balanced overvoltage protector for a dual-wire system comprising a single semiconductor substrate including two breakover thyristors located in sufficiently close proximity so that current in one thyristor effects firing of the other thyristor at a voltage less than its breakover voltage.

Balanced overvoltage protector for a dual-wire system

A semiconductor device having a power switch (12) and a saturation detection diode (13) formed in an upper surface of a semiconductor drift region (11) is provided. The saturation detector diode (13) and the power switch (12) are electrically coupled by the drift region (11). An external signal applied to the detector diode (13) forward biases the detector diode (13) when the drift region (11) potential is below a predetermined voltage and the detector diode (13) becomes reverse biased when the drift region (11) potential is greater than the predetermined voltage.

High power semiconductor device with integral on-state voltage detection

A bidirectional two-terminal ungated thyristor (9) having two wide-base portions (25, 27). The bidirectional two-terminal ungated thyristor (9) has a first semiconductor device having a first narrow-base portion (28) in series with a first wide-base portion (25), and a second semiconductor device having a second narrow-base portion (26) in series with a second wide-base portion (27). A width of the first wide base portion (25) and a width of the second wide base portion (27) are decreased to decrease a total base width. The first and second wide-base portions (25, 27) having a decreased width produce a low forward voltage drop across the bidirectional two-terminal ungated thyristor (9); thus, improving a power dissipation capability of the bidirectional two-terminal ungated thyristor (9).

Bidirectional two-terminal thyristor

A vertical power MOSFET structure having a source and base region which are not shorted together is provided. The source and base region are formed in a semiconductor substrate using a selectively patterned gate stack which is formed on the substrate as a mask. The drift region is formed of a semiconductor material covering a semiconductor substrate. The semiconductor substrate is of the same conductivity type as the drift region for a MOSFET and is of an opposite conductivity type for an IGBT.

Insulated gate semiconductor device with reduced based-to-source

A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.

Conductivity modulated insulated gate semiconductor device

Integrated high voltage transistors having minimum transistor to transistor crosstalk are fabricated in refilled epitaxial tubs, which are formed in a heavily doped substrate. The heavily doped substrate provides the isolation between each transistor, and thus provides for minimum transistor to transistor crosstalk. The voltage capability of the transistor is increased by forming the base surrounding the collector contact in the refilled epitaxial tub.

Integrated high voltage transistors having minimum transistor to

A high voltage semiconductor structure having multiple guard rings, wherein guard rings farthest from a main junction are spaced further from each other than are guard rings closer to the main junction is provided. An enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings, thereby increasing the breakdown voltage of the device. The enhancement region and close guard ring spacing result in a fine gradation of electric field and high punch-through breakdown voltage between guard rings.

High voltage planar edge termination using a punch-through retarding

A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.

Bipolar semiconductor device having a conductive recombination layer

Method of making bipolar semiconductor device having a conductive

An elevated bonding pad suitable for wire or lead frame attachment and having an insulating layer completely over its outer periphery. The structure simplifies the processing required to form an elevated bonding pad, and serves to protect the periphery against bonding damage, and provides protection against corrosion of the bonded encapsulated semiconductor unit.

Elevated edge-protected bonding pedestals for semiconductor devices

A semiconductor p-n junction structure with improved blocking voltage capability. The improvement results from the addition of a doped layer with limited total doping to the main p-n junction. Such a structure is suitable for diodes, transistors, thyristors and the like.

Method of making high voltage semiconductor structure

Magnetically sensitive semiconductor elements suitable for fabrication in monolithic integrated circuits are disclosed. The elements comprise a semiconductor region of one conductivity type with contact means for providing current flow generally parallel to a major axis, a second orthogonal axis for the application of a magnetic field, and yet a third mutually orthogonal axis along which are disposed at least three second type conductivity regions forming in combination with the first major region a transistor structure with differential properties. In some of the embodiments, low magnetic offset is provided by a selfaligning feature, and power comsumption is minimized by a high resistance region in the device.

Semiconductor magnetic transducers

A high-voltage power transistor is hereinafter described which is able to withstand fluences as high as 3 .times. 10.sup.14 neutrons per square centimeter and still be able to operate satisfactorily. The collector may be made essentially half as thick and twice as heavily doped as normally and its base is made in two regions which together are essentially four times as thick as the normal power transistor base region. The base region has a heavily doped upper region and a lower region intermediate the upper heavily doped region and the collector. The doping in the intermediate region is as close to intrinsic as possible, in any event less than about 3 .times. 10.sup.15 impurities per cubic centimeter. The second base region has small width in comparison to the first base region, the ratio of the first to the second being at least about 5 to 1. The base region having the upper heavily doped region and the intermediate or lower low doped region contributes to the higher breakdown voltage which the transistor is able to withstand. The high doping of the collector region essentially lowers that portion of the breakdown voltage achieved by the collector region. Accordingly, it is necessary to transfer certain of this breakdown capability to the base region and this is achieved by using the upper region of heavily doped and an intermediate or lower region of low doping.

High reliability epi-base radiation hardened power transistor

Semiconductor devices, with especial reference to transistors with reduced turn-off times. This improvement includes a low-barrier height metal contact to one of the lightly-doped regions of the device as a replacement for the conventional heavily-doped region or high-low junction structure usually employed for the purpose of providing ohmic contact.

Growing community of inventors

Phoenix, AZ, United States of America

Lowell E Clark