Bull Hn Information Systems, Inc.

Lowell D McCulley

Russell Wayne Guenthner

William A Shelly

Charles P Ryan

Ronald E Lange

Ronald W Yoder

Clinton B Eckard

Wayne R Buzby

David S Edwards

Leonard Rabins

Sidney L Andress

Robert J Baryla

Richard L Demers

Wilbur L Stewart

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.

Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment

In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by utilizing a plurality of sets of registers maintained in a round-robin system. Whenever a transition is made to a higher security environment, a switch is made to a different set of registers. Then, when a transition is made back to the lower security environment, a switch is made back to the previous set of registers. Writes to memory copies of registers are detected, and only those registers whose memory copies have been modified are restored from the memory copy.

Process switching register replication in a data processing system

In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.

System for explicitly referencing a register for its current content when performing processor context switch

In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or 'don't care'. If a field is marked as 'don't care', the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word. If the guarded fields in the first virtual control word align with the 'don't care' fields in the second virtual control word and vice versa, the two virtual control words can be combined into a single control word containing the contents of the guarded fields from both virtual control words, the remaining fields, if any, remaining 'don't care'. This process may be reiterated to determine if the combined control word can be further combined with another virtual control word. In operation, all the functions represented by a combined control word are executed by calling for that single control word stored in the secondary control word memory.

Method for reducing control store space in a VLSI central processor

A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling module includes the steps of: setting an intercept flag when a central processor fault occurs if the fault is to be directed to a preprocessor; establishing a safestore frame which includes information identifying the type of fault and whether the intercept flag is set; and transferring control to the OS fault handling module; then in the OS fault handling module, determining whether the intercept flag is set; if the intercept flag is not set, handling the fault in the OS fault module; if the intercept flag is set, transferring control from the OS fault module to an Intercept Process written in machine language; and handling the fault in the Intercept Process. This renders the resolution of faults due to correctable CPU design errors independent of the OS employed at a given installation and customizable to a given system without the need to revise the OS fault modules for each OS. As each such design error is worked out (e.g., by installing a substitute integrated circuit in which the error has been corrected), the Intercept Process (and CPU firmware) can be modified to remove monitoring and handling for faults due to the corrected error.

Fault intercept and resolution process independent of operating system

In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

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Glendale, AZ, United States of America

Lowell D McCulley