Spansion Llc.

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Monterey Research, LLC

Lovejeet Singh

Shenqing Fang

Kuo-Tung Chang

Hidehiko Shiraiwa

Chih-Yuh Yang

Youseok Suh

Amol Ramesh Joshi

David H Matsumoto

Meng Ding

Tim Thurgate

Harpreet Kaur Sachar

Hapreet Sachar

Scott Allan Bell

Satoshi Torii

Allison Holbrook

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

Self-aligned STI with single poly for manufacturing a flash memory device

An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Integrated circuit memory system employing silicon rich layers

Growing community of inventors

Sunnyvale, CA, United States of America

Lovejeet Singh