Arm Limited

Louise Margaret Jameson

Andrew Mark Nightingale

An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model. Accordingly, by such an approach, the alternative model can take the place of the component model during performance of the selected verification tests. This maintains system integrity of the system under verification, whilst providing a simple and effective mechanism for enabling the alternative model to take the place of the component model for certain specific verification tests, for example when testing corner cases in the design.

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Cambridge, United Kingdom

Louise Margaret Jameson