Sun Microsystems, Inc.

Louise Gu

Cong Quoc Khieu

Chaidir Tjakra

Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes aand b, respectively. In one embodiment, the circuit asynchronously generates a binary code crepresenting an average of the binary codes aand bgenerated by the first and second circuits, respectively.

Average code generation circuit

Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

Variably controlled delay line for read data capture timing window

Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node. The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node. Further, the common node biasing circuit is configured to transmit only AC current to or from the ground node.

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Fremont, CA, United States of America

Louise Gu