Fairchild Semiconductor Corporation

Other

Harris Corporation

Louise E Skurkey

Christopher Boguslaw Kocon

Thomas E Grebs

John M Neilson

Christopher L Rexer

Linda Susan Brush

John Lawrence Benjamin

Richard Douglas Stokes

Gary M Dolny

Nathan Lawrence Kraft

Rodney S Ridley

Jifa Hao

Anup Bhalla

Frank Stensney

Rodney S Ridley, Sr

Christopher Michael Scarba

Chris Gasser

Christopher Boguslow Kocon

In a power semiconductor device , a continuous trench has an outer circumferential portion that includes a field plate and inner portions that carry include one or more gate runners to that the gate runners and the field plate are integral with each other. The trench structure is simpler to form and takes up less surface space that the separate structures of the prior art. The trench is lined with an insulator and further filled with conductive polysilicon and a top insulator.

Buried gate-field termination structure

A trench MOS-gated device has an upper surface and includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core formed of a second dielectric material extending upwardly from the first dielectric material on the trench floor and having lateral and top surfaces. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the lateral and top surfaces of the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface of the device. An interlevel dielectric layer disposed on the upper surface overlies the gate trench and the source region, and a metal layer in electrical contact with the source and body regions overlies the upper surface and the interlevel dielectric layer.

Trench MOSFET with low gate charge

A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.

Method of making a MOS-gated semiconductor device with a single diffusion

A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.

Method of making MOS-gated semiconductor devices

Growing community of inventors

Conyngham, PA, United States of America

Louise E Skurkey