Silicon Storage Technology, Inc.

Louisa Schneider

Hieu Van Tran

Nhan Do

Steven Lemke

Henry A Om'Mani

Thuan Vu

Vipin Tiwari

Xian Liu

Jinho Kim

Yuri Tkachev

Parviz Ghazavi

A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Memory cell array with row direction gap between erase gate lines and dummy floating gates

Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.

Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network

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San Jose, CA, United States of America

Louisa Schneider