Oracle America, Inc.

Sun Microsystems, Inc.

Louis Yonlo Tsien

Tarik Pertev Soydan

Stephen Alan Chessin

Scott W Davenport

Robert Moffett

Tarik P Soydan

A method for fault management. The method includes generating, in firmware of a computer system, a physical resource inventory (PRI) of a plurality of hardware components of the computer system, wherein the PRI defines a hierarchy of the hardware components. The method further includes traversing, by an enumerator executing in a fault manager, the PRI to generate a topology of the plurality of hardware components. The topology is used for fault management of the computer system.

Method and system for platform independent fault management

A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.

Prediction and prevention of uncorrectable memory errors

A memory error injector is defined to include a connector for enabling connection with a standard memory module receptacle. The memory error injector also includes a standard memory block defined to interface with the connector and operate in accordance with a standard memory specification. The memory error injector further includes error injection logic defined to force data transmitted to or from a specified memory location within the standard memory block to a fixed state, for a first number of access cycles addressed to the specified memory location. The error injection logic is defined to force the data to the fixed state during transmission of the data between the connector and the standard memory block.

Memory error injector and associated methods

One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory location in a main memory by a first processor, wherein the correctable error is detected by error detection and correction circuitry. Next, the system reads tag bits for a cache line associated with the memory location, wherein the tag bits contain address information for the cache line, as well as state information indicating a coherency protocol state for the cache line. The system then tests the memory location by causing the first processor to perform read and write operations to the memory location to produce test results. Finally, the system uses the test results and the tag bits to determine the cause of the correctable error, if possible.

Growing community of inventors

Watertown, MA, United States of America

Louis Yonlo Tsien