Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux

Societe Pour L'etude Et La Fabrication Des Circuits Integres Speciaux

Louis Tallaron

Jean C Bertails

Cristian Perrin

Jean P Bertails

The invention relates to a detector of the mean level of a signal particularly intended to indicate whether an expected alternating signal is absent or present. This detector uses an analog comparator, a digital counter and a converter for establishing an analog signal to be compared with the expected rectified signal. The counter content oscillates round the mean value of the rectified signal. The counter serves as a digital integrator for the sign of the difference between the input signal and the content of the counter, in such a way that on average the input signal is just as often above as below the counter content. The digital - analog conversion can take place with the aid of switched capacitors.

Analog signal level detector

A data transfer bus preloading circuit including a large sized transistor r ensuring rapid bus conductor preloading. This transistor is conductive at the beginning of the preloading step proper, but is blocked as the bus voltage reaches the desired preload value which corresponds to the sum of the respective threshold voltages of two other transistors of the circuit. The circuit includes five field effect transistors, two supply terminals, a preloading control input terminal and a preloading inhibiting input terminal. The large size transistor is connected between a first supply terminal and the output terminal of the circuit. A second transistor is connected between the gates of the first and third transistors. The gate of the second transistor is connected to the preloading control input terminal. The third transistor is connected between the source terminal and the fifth transistor. The gate and source of the third transistor are connected together. The fourth transistor is connected between the ground supply terminal and the gate of the first transistor. The gate of the fourth transistor is connected to the preloading inhibiting input terminal. The fifth transistor is connected between the third transistor and the ground supply terminal. The gate of the fifth transistor is connected to the output of the circuit. It is also possible to add a sixth transistor between the fifth transistor and the ground supply terminal with the drain and gate of this transistor being connected together.

Logic data transfer bus preloading circuit

This invention concerns an integrated-circuit amplifier incorporating CMOS (metal oxide semiconductor) technology, which amplifiers are capable of supplying a standardized 600 Ohm load, for example. This amplifier functions in class AB, and its output stage comprises an NPN bipolar transistor and an N-channel MOS transistor, connected in series in the same way as a conventional push-pull stage. The NPN transistor is controlled directly at its base by the signal for amplification. The control grid of the MOS transistor receives the output signal from a differential amplifier, one input of which is connected to the amplifier output S, the other input being connected to the emitter of another bipolar transistor, the base of which receives the signal for amplification.

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St. Egreve, France

Louis Tallaron