Exponential Technology, Inc.

Louis S Lederer

James S Blomgren

Peter J Vigil

A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU's. When 3 CPU's are on the die, their outputs are compared during a self-testing mode. If outputs from all three CPU's match, then no error is detected. When two CPU's outputs match, but a third CPU's output mismatches, then the third CPU is faulty. The output compared from each CPU is a serial scan-chain shift-out, parity from internal test points, and a result written to the shared cache. Each CPU core has a serial scan chain. The serial scan chain strings together most flip-flops in the CPU core into a serial chain. A test clock is pulsed to shift out the data from these flip-flops. During each test clock period, the serial data from each CPU is compared to the serial data from other CPU's. Internal test points within each CPU core are defined at high traffic areas in the pipeline. Parity is generated from these internal test points, and the parity from one CPU is compared to that for other CPU's during each CPU clock cycle. The results from each CPU core written back to the shared cache are also compared, and arbitration allows one CPU to write the result to the shared cache while results from other CPU's are discarded. A self-test circuit on the die accumulates errors for each CPU and reports these errors to an inexpensive external tester.

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Sunnyvale, CA, United States of America

Louis S Lederer