Dallas Semiconductor Corporation

Louis Rodriguez

Kevin E Deierling

Clark R Williams

Bradley M Harrington

A timekeeping integrated circuit with devices partitioned into areas with different power supplies and level translators between the areas; the level translators use a memory cell for isolation and to shorten the signal active time for low power consumption. Also a one-wire communication port with low power input buffers may be used to detect very slowly varying voltages. The input buffers include staged decreasing resistors as a power dissipation limitation.

Low power module

A low-power timekeeping integrated circuit, using a double-buffered memory architecture: The user can freely read from user memory at any time, and an internal clock periodically updates a set of timekeeping registers. Transfer from the timekeeping registers to user memory (for update of the data) is performed as a block transfer, asynchronously and invisibly to the user. A special timing-window requirement is used to avoid access collision problems: each edge of the one-hertz oscillator signal is delayed slightly, and it is the delayed signal which actually clocks the update to the timekeeping registers. After a further small delay (long enough to allow for worst-case ripple-through delays in the timekeeping registers), a latched signal (NO.sub.-- RIPPLE, in the presently preferred embodiment) is driven active. The signal NO.sub.-- RIPPLE shows that any rippling has been completed and that access is safe. Thus, transfer will occur or not, but will never be cut short. When the user attempts to access the chip, the logic signal NO.sub.-- RIPPLE is sampled. If NO.sub.-- RIPPLE is not active, no transfers from timekeeping registers to the user memory is permitted, for as long as the user is accessing the chip. Whenever the user finishes an access, an update is automatically activated. Thus, in this scheme, the chip logic, while avoiding any updating during an access, will always provide the most current data into the user accessible registers, whenever possible.

Double-buffered systems and methods

An integrated circuit with power-up-warning circuitry wherein time integration and voltage level testing are done sequentially instead of simultaneously. A reference voltage is generated by current sourced to a reference voltage circuit, and this reference voltage is used as follows: An inverter receives the reference voltage as an input, and switches when the power supply becomes high enough that the reference voltage appears as a 'low' level. When this inverter switches, current begins to be sourced to a timing capacitor. After the timing capacitor has charged up to a predetermined level, the current source to the reference-voltage node is turned off, and the power-up-warning signal (which has been driven high by output buffers) is turned off.

Growing community of inventors

Dallas, TX, United States of America

Louis Rodriguez