Compaq Computer Corporation, Inc.

Louis R Gagliardi

Siamak Tavallaei

Joseph P Miller

Darren John Cepulis

Gordon R Clark

George H Myers

Evan J Bontemps

A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols. The server controller snoops display data written from the host CPU to the video controller and mirrors the display data upon buffers within the server controller. Information within the buffers can be called upon by a remotely situated administrator regardless of whether server power is lost in the interim.

Server controller configured to snoop and receive a duplicative copy of display data presented to a video controller

A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

PCI hot spare capability for failed components

A media detection system that detects an external device coupled to a port of a network device and that establishes a working communication link. The media detection system includes a port connector including first and second contact sets and a physical layer device which includes a transmit output and a receive input. The physical layer device monitors its receive input for communication signals and provides a link detect signal indicative thereof. The media detection system further includes a select circuit that selectively couples the transmit output and the receive input of the physical layer device to the first and second contact sets, respectively, of the port connector in a first state and crosses the connection in a second state. A control circuit is provided that toggles the select circuit between the first and second states until the link detect signal indicates reception of communication signals, whereupon the control circuit holds the select circuit in the particular state in which communication signals were detected. If the link signal is negated thereby indicating subsequent loss of the communication signals, the control circuit preferably returns to the toggle mode to detect a new device coupled to the port.

Method and apparatus for automatically detecting media connected to a

A multiprocessor computer system handles the failure of one or more of its processors without totally disabling the system. On power up, all of the CPUs are deactivated except for a CPU in a first physical slot. The power on self test routines review a log of errors and determine if certain critical errors have previously occurred. If so, the CPU in the first physical slot halts operation entirely. If the CPU in the first physical slot is not functioning properly or is halted, the hardware then awakens a CPU in a second physical slot, designates it as the first logical CPU, and the CPU then performs similar diagnostic checks. If it fails, the hardware again tries a third physical CPU and so on. When one CPU passes the initial error review, it proceeds with initialization of the computer system and performs further self testing. If it functions properly, it is designated as the first logical CPU, and retains its designation until the power is cycled. This first logical CPU then awakens the remaining CPUs and boots the rest of the system. If it fails this later self testing by having certain critical errors occur, the logical CPU 0 designation is transferred to another active CPU and the old CPU is halted. The new CPU commences operation effectively where the old CPU halted, so that system initialization is continued not restarted. The power on self test routines then further test the CPU in the first physical slot. Thus, if at least one CPU is operational, the computer system boots and operates.

Growing community of inventors

Tomball, TX, United States of America

Louis R Gagliardi