U.S. Philips Corporation

Louis Praamsma

Stephen J Battersby

Roger Cuppens

Teunis Hemanus Uittenbogaard

Gerrit-Jan Hemink

Jan Middelhoek

Rutger C Wijburg

Wilhelmus G Voncken

The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (,) and a drain region (,) and, between said regions, a channel region (,) above which a gate region (,) is located. The gate region (,) is formed by applying an insulating layer (,) to the semiconductor body and providing this insulating layer with a stepped portion (,) in the thickness direction, whereafter a conductive layer (,) is applied to the surface of the semiconductor body (,), which layer is substantially removed again by etching, so that a part (,A) of the conductive layer (,), which part forms part of the gate region (,) and which lies against the stepped portion (,), remains intact. In a method in accordance with the invention, the source region (,) and the drain region (,) are formed before the insulating layer (,) is provided, and after the provision of the part (,A) of the gate region (,), which part is formed from the conductive layer (,), the surface of the semiconductor body (,) is made flat by applying a further insulating layer (,) next to the stepped portion (,). Such a method enables a T-shaped gate region (,) to be manufactured in a simple manner, said gate region comprising a very short vertical part (,A) of, for example, polycrystalline silicon and an overlying wider horizontal part of, for example, aluminium. Such a transistor has excellent high-frequency properties. In a preferred embodiment, the stepped portion (,) is formed by providing the insulating layer with a recess (,) whose side walls are situated above the source region (,) and the channel region (,). In a particularly simple variant, a &ldquo;parasitic&rdquo; gate region (,) is subsequently formed above the source region (,), which is not objectionable. The recess (,) can further be used in the formation of LDMOST whose source region (,) can be provided with an extension (,A).

Method of manufacturing a semiconductor device comprising a field effect transistor

A semiconductor device with a semiconductor body (3) including a surface region (5) of a first conductivity type which adjoins a surface (4) and in which a field effect transistor (1) with insulated gate (6) is provided. The field effect transistor (1) has source and drain regions (7, 8, respectively) of the second, opposed conductivity type situated in the surface region (5), and a channel region (9) of the first conductivity type situated between the source and drain regions. A metal gate electrode (6) separated from the channel region (9) by an insulating layer (10) is provided over the channel region (9) and is provided with a protection device (2) against excessive voltages applied to the gate electrode (6). According to the invention, the surface (4) of the semiconductor body (3) is provided with a locally recessed field oxide (15), and the protection device (2) includes a lateral bipolar transistor with collector and emitter regions (16, 17, respectively) of the second conductivity type which are more strongly doped than the surface region (5) and which adjoin the surface (4) and the field oxide (15), and with a base region (18) of the first conductivity type which is more strongly doped than the surface region (5) and which lies below the field oxide (15), the collector region (16) being electrically connected to the gate electrode (6) and the emitter region (17) being electrically connected to the source region (7). It is achieved thereby that the field effect transistor (1) can switch high frequencies much more quickly.

High-frequency semiconductor device with protection device

A dual-gate insulated gate field effect device (1) such as a MOS tetrode has an active device area (3) in which adjacent source regions (5) are separated by and spaced apart from an intervening drain region (6) to define a respective conduction channel region (7) between each source and drain region (5 and 6). An insulated gate structure (10) has first insulated gate sections (11) forming an inner insulated gate (110) connected so as to surround each drain region 6 and second insulated gate sections (12) provided between the first insulated gate sections (11) and the source regions (5) and forming an outer insulated gate (120). Ends (11a,12a) of the insulated gate sections (11 and 12) extend onto the surrounding field oxide (4) to connect with respective first and gate conductors (13 and 14). Each drain region (6) is associated with an additional source region (50) spaced apart from the drain region (6) in a direction parallel to the width W of the conduction channel regions to define an additional conduction channel region. The second insulated gate sections (12) are connected to provide an area of insulated gate (12b) between each additional source region (50) and the associated drain region (6). This substantially eliminates leakage currents and enables the use of a design in which parasitic capacitances are reduced.

Dual-gate insulated gate field effect device

A controllable amplifier circuit includes, successively, in a cascode arrangement between a power supply voltage and ground, a control transistor and a field effect amplifier transistor having a control input for applying a gain control signal thereto and a gate input for applying an input signal thereto, respectively, via which control transistor the field effect amplifier transistor supplies an output signal to a signal output of the controllable amplifier circuit. The control transistor varies the working point of the field effect amplifier transistor in the ohmic range in dependence upon the gain control signal, at least in a part of the control range of the gain control signal. The circuit can be used with a low power supply voltage because the controllable amplifier circuit includes a controllable bias circuit which is coupled to the gate input of the field effect amplifier transistor for applying a controllable bias voltage thereto. This voltage varies in the opposite direction to the gain control signal mainly in said part of the control range.

Controllable amplifier circuit

Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern. A compact cell array layout can be formed with a common connection region for the injector regions of two adjacent cells and for either a source or drain region of four other adjacent cells. The control gate and an erase gate may both be coupled in the same manner to the charge-storage region, and the cell can be operated with complementary voltage levels for writing and erasing. A feed-back mechanism with the start of injection from the punch-through and injector regions can provide a well-defined charge level limit for the erasure.

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Nijmegen, Netherlands

Louis Praamsma