Texas Instruments Corporation

Louis N Hutter

John P Erdeljac

Jeffrey P Smith

Marco Corsi

James Robert Todd

Imran Khan

Taylor R Efland

Jozef C Mitros

John Kenneth Arch

William E Nehrer

Michael C Smayling

Donald Charles Abbott

Joe R Trogolo

Chi-Cheong Shen

Charles E Williams

Konrad Wagensohner

Quang X Mai

M Ali Khatibzadeh

Walter Bucksch

Peter S Ying

James D Goon

Mary Ann Murphy

Shiu-Hang Yan

Sameer P Pendharkar

Masashi Hashimoto

Han-Tzong Yuan

Stuart M Jacobsen

Philipp Steinmann

Jau-Yuann Yang

Chin-Yu Tsai

Weidong Tian

Frank L Thiel

Georges Falessi

Milton Lee Buschbom

Michael R Kay

C Matthew Thompson

Fred D Bailey

Arnold C Conway

Gopal K Rao

Mark E Gibson

AnhKim Duong

Susan S Kearney

Manuel Torreno

S Shivaling Mahant-Shetti

James (Bob) Todd

A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Semiconductor device with an analog capacitor

System and method for forming a semiconductor with an analog capacitor using fewer structure steps

A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via ( ) etch and fill, the thin film resistor material ( ) is deposited. The metal interconnect layer ( ) is then deposited, including any barrier layers desired. The metal leads ( ) are then etched together with the shape of the thin film resistor ( ). The metal ( ) over the thin film resistor ( ) is then removed.

Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect

The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.

Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis

An integrated circuit device ( ) with a bonding surface ( ) directly over its active circuitry, and a method of making such integrated circuits (FIGS. A- E). To make the bonding surface ( ), a wafer ( ) is provided with vias ( ) to its metallization layer ( ) and then coated with a seed metal layer ( ). A plating pattern ( ) is formed on the wafer ( ), exposing portions of the seed metal layer ( ) and blocking the rest of the seed metal layer ( ). These exposed portions are plated with successive metal layers ( ), thereby forming a bonding surface ( ) having a number of layered stacks ( ) that fill the vias ( ). The plating pattern and the nonplated portions of the seed metal layer ( ) are then removed.

Integrated circuit with bonding layer over active circuitry

A tunnel diode construction for an EEPROM device , and method for making it are shown. A tank is provided at a surface of a semiconductor substrate containing a doped diffused tunnel region . A layer of insulation is provided over the surface of the substrate with a first thickness to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness elsewhere. A conducting floating gate is provided above the doped diffused tunnel region and at least part of the tank , on the layer of insulation . The floating gate extends over the oxide beyond the lateral boundaries of the doped diffused tunnel region in every direction to terminate over the second thickness of oxide over the tank . To complete the EEPROM device , an MOS transistor having source and drain doped regions provided in the substrate , with a portion of the floating gate capacitively coupled to a control gate and extending over at least part of a channel region of the MOS device.

Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region

Capacitors for integrated circuits with a common polysilicon layer for both MOS gates ( ) and capacitor ( ) lower plates but with implanted doping for the gates and masked diffusive doping for the capacitor plates.

Integrated circuit capacitor and method

An LDMOS device ( ) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells ( ). The Dwell ( ) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region ( ), which permits the n-type region of the Dwell to diffuse under the gate region ( ) an sufficient distance to eliminate misalignment effects.

LDMOS power device with oversized dwell

A method for making an isolated NMOS transistor ( ) in a BiCMOS process includes forming an N&minus; conductivity type DUF layer ( ) in a P conductivity type semiconductor substrate ( ), followed by forming alternate contiguous N&plus; and P conductivity type buried regions ( ) in the substrate ( ). A layer of substantially intrinsic semiconductor material ( ) is then formed on the substrate ( ) in which alternate and contiguous N and P conductivity type wells ( ) are formed, respectively above and extending to the N&plus; and P conductivity type buried regions ( ). Finally, NMOS source and drain regions ( ) are formed in at least one of the P conductivity type wells ( ). The method is preferably performed concurrently with the construction of a bipolar transistor structure ( ) elsewhere on the substrate ( ). More particularly, the steps of forming the P conductivity type buried layer ( ) may be performed a part of a simultaneous formation of a collector element of the PNP transistor ( ) elsewhere on the substrate ( ).

Isolated NMOS transistor fabricated in a digital BiCMOS process

A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region of a bipolar transistor and a p-well of an n-channel MOS transistor; and forming in a single implantation step a collector contact well of a bipolar transistor and an n-well of a p-channel MOS transistor.

Merged bipolar and CMOS circuit and method

A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Metalization outside protective overcoat for improved capacitors and inductors

A power field effect transistor is disclosed that includes polysilicon gate bodies (,) and (,), which includes platinum silicide contact layers (,) and (,) disposed on the outer surfaces of bodies (,) and (,), respectively. In addition, the device comprises an n&plus;drain region (,) which also has a platinum silicide drain contact layer (,) formed on its outer surface and platinum silicide source contact layers (,) and (,). During formation, sidewall spacers (,) and (,), as well as mask bodies (,) and (,) are used to ensure that platinum silicide layer (,) spaced apart from both gate bodies (,) and (,) and platinum silicide gate contact layers (,) and (,).

Power transistor with silicided gate and contacts

Metallization outside protective overcoat for improved capacitors and inductors

A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.

Transistor with increased operating voltage and method of fabrication

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Growing community of inventors

Richardson, TX, United States of America

Louis N Hutter