Apple Inc.

Raytheon Company

Hrl Laboratories, LLC

The Boeing Company

Louis Luh

Eric G Smith

Keh-Chung Wang

William C Athas

Miroslav Micovic

David H Chow

Wah S Wong

Heather R Sullens

Don Hitko

Cheng Kai Chen

Jun Qi

Chaohao Wang

Paolo Sacchetto

Chun-Yao Huang

Marc Albrecht

P Jeffrey Ungar

Matthias Knoth

Rohit Kumar

Todd S Kaplan

Jun Jiang

Patrick R Gill

Key-Chung Wang

Eric Smith

Systems and methods for operating a display by dynamically determining a refresh rate for the display. In certain implementations, a processor determines a number of pixels having medium grayscale levels from a histogram for the image. If the number does not exceed a threshold, the processor sets a refresh rate for the display to a first refresh rate. In certain implementations, if the number exceeds a threshold, the processor may set the refresh rate for the display to a second refresh rate. Moreover, the first refresh rate may be lower than the second threshold. In some implementations, the image may be analyzed by subdividing the image into blocks and determining a refresh rate based on grayscale levels or distributions in the blocks. Based on the analysis of the blocks, a corresponding refresh rate may be selected.

Content dependent display variable refresh rate

The disclosed embodiments provide a system that operates a power supply. During operation, the system obtains power states of two or more loads coupled to two or more power converters in the power supply. Next, the system generates one or more control signals for a set of switching mechanisms to configure a coupling of the two or more loads to the two or more power converters through the switching mechanisms based on the power states.

Reconfigurable multiple-output power-delivery system

The disclosed embodiments provide a system that operates a power supply. During operation, the system disposes a first switching mechanism between a first output of a first power converter and two or more loads. Next, the system obtains two or more error signals for the two or more loads, wherein each error signal from the two or more error signals represents a difference between a load voltage of a load from the two or more loads and a first reference voltage for the load from a first set of reference voltages for driving the two or more loads using the first power converter. The system then uses the first switching mechanism to couple the load with a largest error signal from the two or more error signals to the first output.

Power delivery in a multiple-output system

Embodiments of an adapter are disclosed that include a rectifier with an input and an output coupled to a step-down transformer with a primary coil and a secondary coil, wherein the primary coil is coupled to the output of the rectifier. A step-up converter is coupled to the secondary coil.

Power adapter with a step-down transformer and a voltage step-up circuit

In some embodiments, a system may include at least one voltage controller. At least one of the voltage controllers may assess, during use, an occurrence of a predetermined condition. In some embodiments, the system may include an at least first capacitor. The at least first capacitor may be coupled to at least one of the voltage controllers such that at least one of the voltage controllers engages the at least first capacitor to supply additional current when the predetermined condition occurs. When the increase in current is no longer required the at least first capacitor may be disengaged. The at least first capacitor may be charged when disengaged until a predetermined capacity.

Active peak power management of a high performance embedded microprocessor cluster

One gate driver includes an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of a display. An input node of the gate driver is configured to receive an input signal. The gate driver includes a first field-effect transistor (FET) having a gate, a drain, and a source. The drain may be coupled to the input node and the source may be coupled to the output node. The gate driver also includes a second FET having a gate, a drain, and a source. The drain may be coupled to the input node. The gate driver includes a capacitor having a first end coupled to the gates of the FETs and a second end coupled to the source of the second FET. Using the gate driver power consumption of the display may be reduced.

Devices and methods for reducing power consumption and size of gate drivers

An adapter for electrical power that includes a rectifier coupled to a transformer with a primary coil and a secondary coil. The secondary coil includes a first end tap, a second end tap, and a center tap. A first switch is coupled between the first end tap and a primary side ground. A second switch is coupled between the second end tap and the primary side ground. A controller is coupled to the first switch and to the second switch so that during one or more intervals, the first switch and the second switch are alternately open and closed a predetermined number of times, wherein the initial switch closed each interval alternates between the first switch and the second switch, and after the predetermined number of times, both the first switch and the second switch are opened for a predetermined time period.

Controlling an adapter transformer voltage

Embodiments of an adapter are disclosed that include a transformer with a primary coil coupled to an H-bridge. The H-bridge is controlled by a control circuit that controls a voltage across the primary coil using the H-bridge, and the control circuit is configured to control the H-bridge so that during each of one or more intervals, a first voltage pulse is applied across the primary coil in a start direction, wherein the start direction alternates between a first direction and a second direction each interval. Then, a direction of subsequent voltage pulses across the primary coil is alternated between the first direction and the second direction a predetermined number of times. After the predetermined number of times, a last voltage pulse is applied across the primary coil; then, voltage across the primary coil is reduced to zero for a predetermined time.

A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.

Integrated structure with transistors and schottky diodes and process for fabricating the same

Integrated structure with transistors and Schottky diodes and process for fabricating the same

A sample-and-hold circuit includes a transconductance cell and an inductive-capacitive (L-C) resonator circuit acting as a bandpass filter.

Bandpass sample-and-hold circuit

The use of a dynamic current bias technique to dynamically bias a voltage switch of a sample-and-hold circuit is disclosed. Dynamically biasing the voltage switch mitigates nonlinear distortion caused by V(V) variation during charging and discharging the holding capacitor of the sample-and-hold circuit The bandwidth of the sample-and-hold circuit is enhanced.

High speed sample-and-hold circuit

A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.

Comparator with resonant tunneling diodes

A Q enhancement circuit and method. In a most general embodiment, the inventive circuit is adapted for use with a component having a parasitic resistance Rand a first resistance Rdisposed in series with the component and an arrangement for making the resistance a negative resistance. In the illustrative embodiment, first and second inductors constitute the components for which Q enhancement is effected. A resistance Ris disposed in series with the first inductor and is equal to the parasitic resistance Rthereof. Likewise, a second resistance Ris disposed in series with the second inductor and is equal to the parasitic resistance Rthereof. The Q enhancement circuit further includes a first transistor Qand a second transistor Q.

Q enhancement circuit and method

A mismatch shaped analog to digital converter. The novel analog to digital converter includes a first circuit for providing a plurality of reference voltages, a plurality of comparators adapted to compare an input signal with the reference voltages, and a second circuit for randomizing connections between the reference voltages and the comparators. The connections are randomized such that noise caused by mismatch errors is spectrally shaped according to a desired noise-shaping characteristic. In an illustrative embodiment, the second circuit includes a noise-shaping circuit comprised of a plurality of Delta-Sigma modulators for generating one or more control signals, and a router for connecting the reference voltages to the comparators in accordance with the control signals. The mismatch shaped analog to digital converter can be used within a Delta-Sigma modulator to shape noise caused by mismatch errors in the feedback digital to analog converter.

Growing community of inventors

Sunnyvale, CA, United States of America

Louis Luh