International Business Machines Corporation

Other

Globalfoundries Inc.

Louis Lu-Chen Hsu

Jack Allan Mandelman

William R Tonti

Chih-Chao Yang

Kangguo Cheng

Lawrence Alfred Clevenger

Ping-Chuan Wang

Howard Hao Chen

James Stephen Mason

Li-Kong Wang

Hayden C Cranford, Jr

Zhijian Yang

Keith Kwong Hon Wong

Cyril Cabral, Jr

Carl John Radens

Haining S Yang

Mukta G Farooq

Kai D Feng

Fariborz Assaderaghi

Brian Joseph Greene

Chun-Yung Sung

Huilong Zhu

Timothy Joseph Dalton

Toshiaki Kirihata

John Anthony Fitzsimmons

Roger Allen Booth, Jr

Michael Anthony Sorna

Rama Divakaruni

Xiaojin Wei

Dale E Pontius

Gregory J Fredeman

Xu Ouyang

Yujun Li

Karl David Selander

Steven John Zier

Chorng-Lii Hwang

Hibourahima Camara

Jong-Ru Guo

Daniel C Edelstein

Rajiv V Joshi

Haizhou Yin

John Edward Sheets, Ii

Herbert Lei Ho

William Paul Hovis

Anthony Richard Bonaccio

Wagdi William Abadeer

Chandrasekhar Narayan

Xinhui Wang

Matthew R Wordeman

Joseph F Shepard

Heinz Hoenigschmid

Brian L Ji

David R Hanson

William Francis Landers

Minhan Chen

Joseph Natonio

Manu J Tejwani

Richard Michael Parent

James D Rockrohr

Scott R Stiffler

Charlie Chornglii Hwang

Gareth John Nicholls

Edward R Pillai

Ishtiaq Ahsan

Westerfield John Ficken

John E Andersen

Philip J Murfet

Joseph O Marsh

Keith Kwong-Hon Wong

Samuel Taylor Ray

Edward J Vishnesky

Jong-ru Guo

Toshio Mii

Jack C Chu

Donna S Zupanski-Nielson

Carl D Radens

Vidhya c/o Ibm United Kingdom Limited Intellectual Property Law Ramachandran

Kai Di Feng

A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

3D chip stack having encapsulated chip-in-chip

Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Forming semiconductor chip connections

A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Layered structure with fuse

Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Method of fabricating field effect transistors with low k sidewall spacers

Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

FinFET with reduced gate to fin overlay sensitivity

A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

Electronic fuses in semiconductor integrated circuits

Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

3D chip-stack with fuse-type through silicon via

An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.

Active inductor for ASIC application

The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.

Thermoelectric 3D cooling

Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Structures incorporating interconnect structures with improved electromigration resistance

Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.

Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering

Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).

Contact forming method and related semiconductor device

In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.

Dielectric material with a reduced dielectric constant and methods of manufacturing the same

A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.

Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate

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Fishkill, NY, United States of America

Louis Lu-Chen Hsu