International Business Machines Corporation

Other

Siemens Aktiengesellschaft

Infineon Technologies North America Corp.

Louis L Hsu

Li-Kong Wang

Jack Allan Mandelman

Rajiv V Joshi

Lawrence Alfred Clevenger

Carl John Radens

Chih-Chao Yang

Chang-Ming Hsieh

William R Tonti

Howard Hao Chen

Seiki Ogura

Kwong Hon Wong

Michael Anthony Sorna

Joseph F Shepard

Fariborz Assaderaghi

Joseph Francis Shepard, Jr

Timothy Joseph Dalton

Keith Kwong Hon Wong

Toshiaki Kirihata

Jeffrey P Gambino

Klaus D Beyer

John Atkinson Fifield

Wayne Frederick Ellis

Jerome J Cuomo

Hormazdyar M Dalal

Kangguo Cheng

Brian L Ji

Jente Benedict Kuang

Russell J Houghton

James Stephen Mason

Ping-Chuan Wang

Hayden C Cranford, Jr

Matthew R Wordeman

Gregory J Fredeman

Oleg Gluschenkov

Dureseti Chidambarrao

Mukta G Farooq

Jack Oon Chu

Conal Eugene Murray

David Edward Kotecki

Nivo Rovedo

Cyril Cabral, Jr

Wolfgang Sauter

Michael Patrick Chudzik

Stephen Victor Kosonocky

Robert C Wong

Wei Hwang

Chun-Yung Sung

Timothy A Brunner

Vidhya Ramachandran

Gunther Lehmann

Ghavam G Shahidi

Chung H Lam

Claude Louis Bertin

Richard C Chu

Gary Bela Bronner

Deborah A Neumayer

Chandrasekhar Narayan

K Paul Muller

Subhash Laxman Shinde

Zhijian Yang

Henning Haffner

Johann Alsmeier

Derek Brian Dove

Tin-Chee Lo

David B Goland

Daniel C Edelstein

Steven H Voldman

Ramachandra Divakaruni

Terence B Hook

Sang Hoo Dhong

John Edward Sheets, Ii

Fei Liu

Dominic Joseph Schepis

Kai D Feng

John Anthony Fitzsimmons

Robert H Dennard

Lawrence Shungwei Mok

William Vincent Huott

Yuen H Chan

John Christopher Arnold

Michael C Gaidis

Paul Christian Parries

Krishna Seshan

Leathen Shi

James A Culp

Werner A Rausch

Fook-Luen Heng

Gerd Frankowsky

Hiroyuki Akatsu

Heinz Hoenigschmid

Kathryn Wilder Guarini

Seshadri Subbanna

David R Hanson

William Francis Landers

Dan Moy

Christopher Carr Parks

Azeez Jennudin Bhavnagarwala

Christy Sensenich Tyberg

Seongwon Kim

Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Forming semiconductor chip connections

A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

Simultaneously forming a through silicon via and a deep trench structure

A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Modularized three-dimensional capacitor array

Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications

A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Interconnect structure containing various capping materials for programmable electrical fuses

An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

Redundancy design with electro-migration immunity and method of manufacture

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Interconnect structure containing various capping materials for electrical fuse and other related applications

Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

FinFET with reduced gate to fin overlay sensitivity

Method for simultaneously forming a through silicon via and a deep trench structure

Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Programmable anti-fuse structures with conductive material islands

A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

Leakage sensor and switch device for deep-trench capacitor array

Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

Techniques for impeding reverse engineering

Structure for interconnect structure containing various capping materials for electrical fuse and other related applications

Growing community of inventors

Fishkill, NY, United States of America

Louis L Hsu