International Business Machines Corporation

Other

Louis L C Hsu

Lawrence Alfred Clevenger

Chih-Chao Yang

Carl John Radens

Timothy Joseph Dalton

Michael C Gaidis

Rajiv V Joshi

Keith Kwong Hon Wong

Chung H Lam

Ping-Chuan Wang

John Kenneth DeBrosse

Brian L Ji

Zhijian Yang

Jeremy K Stephens

Michael Lester Wise

Keith Kwong-Hon Wong

Jack Allan Mandelman

Matthew Earl Colburn

Matthew R Wordeman

Oliver Weinfurtner

Li-Kong Wang

Chandrasekhar Narayan

Hon-Sum Philip Wong

Kaushik Chanda

Larry Clevenger

John K Debrosse

Kevin P Guay

A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.

Self-repair integrated circuit and repair method

A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

High density planar magnetic domain wall memory apparatus

A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.

Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed.

Write operations for phase-change-material memory

A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.

Structure for stochastic integrated circuit personalization

A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Method for forming slot via bitline for MRAM devices

A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Addressable hierarchical metal wire test methodology

Method and structure for forming slot via bitline for MRAM devices

A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

Semiconductor constructions and semiconductor device fabrication methods

Structure and method for stochastic integrated circuit personalization

A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.

Method of forming high density planar magnetic domain wall memory

A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

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Fishkill, NY, United States of America

Louis L C Hsu