Texas Instruments Corporation

Louis J Izzi

William Robert Krenik

Chenwei J Yin

Richard E Downing

Henry T Yung

Karl M Guttag

Richard D Simpson

Jeffrey L Nye

Jerry R Van Aken

James F Hollander

Edison H Chiu

Carrell R Killebrew, Jr

Mike Asal

Richard C Nail

A method is provided for accessing data stored in memory (76). First data appearing at outputs (102) of memory (76) are read during a first reading cycle in a sequence of reading cycles, the first data retrieved from a first location in memory (76) corresponding to a first address. At the end of the first reading cycle, the first address is stepped to produce a second address corresponding to a second location in memory (76). During an idle period following the first reading cycle and prior to a second reading cycle occurring next in the sequence of reading cycles, second data is prefetched from the second location in memory (76) such that the second data appears at the bitlines (102) of memory (76) at the start of the second reading cycle.

Sequential access memories, systems and methods

Test circuitry (90) is provided which includes a multiplexer (118) for selectively receiving multiple bit control words defining test functions to be executed by said test circuitry and for outputting data from said test circuitry. A plurality of digital data inputs (96) are provided for receiving multiple bit words of digital data and a plurality of analog data inputs (98) are provided for receiving analog data. A register (120) is coupled to multiplexer (118) for storing a one of the multiple bit words received by multiplexer (118). Control circuitry (122) is coupled to register (120) for controlling execution of the test function defined by the control word being held in register (120). First test circuitry (112) is coupled to digital data inputs (96) and control circuitry (122) for passing digital data words received at digital data inputs (96) to multiplexer (118) for output in response to a first control word of said control words being held in register (120).

Test circuitry, systems and methods

An integrated circuit capacitor has a semiconductor die and a plurality of field effect transistors fabricated on the die and having gates, sources and drains. The gates are connected to each other as one side of the capacitor. The sources and drains are connected together as another side of the capacitor. A color palette has a die with circuitry including a dot clock buffer with transistors connected to supply rails and the integrated circuit capacitor having a plurality of the parallel-connected field effect transistors connected across the supply rails. The dot clock buffer has an output distributed directly to the rest of the circuitry. Other capacitors, buffers, systems and methods are also disclosed.

Integrated circuit capacitors, buffers, systems and methods

An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Graphics system including an output buffer circuit with controlled

A frame buffer is provided, including a plurality of input nodes and a plurality of multiplexing circuits. Each multiplexing circuit has a first input coupled to a respective input node. First control circuitry is provided for selectively coupling a second input of each multiplexer circuit to outputs of others of the multiplexing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the first and second inputs.

Frame buffer, systems and methods

Frame buffer, method and circuit

A clock control circuit 84 is provided which includes circuitry 98 for selecting a master clock from among at least two input clocks provided to clock control circuit 94, the selection made in response to master clock selection control signals. Circuitry 104 is coupled to circuitry for selecting 98 for providing at least first and second divided down clocks each being of a different divide ratio of the master clock. Circuitry 108 is coupled to circuitry for providing divided down clocks 104 for selecting an output clock from between at least the first and second divided down clocks in response to output clock selection control signals received by clock control circuit 84. Circuitry 120 is provided coupled to circuitry for selecting an output clock 108 for selectively controlling the output of the output clock, circuitry for controlling output clock 120 enabling output of the output clock in response to a first output clock control signal received by clock control circuitry 84 and disabling output of the output clock in response to a second output clock output control signal received by clock control circuit 84. Circuitry 120 is further operable to selectively output an additional output clock cycle in response to a control signal during a period when circuitry for controlling 120 has disabled output of the output clock.

Color palette timing and control with circuitry for producing an

A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.

Video interface palette, systems and method

A color palette is provided having a plurality input terminals for receiving a plurality of bits of data having an order. A two color path is included which comprises first circuitry coupled to the input terminals for selectively reversing the order of the plurality of bits of data. Second circuitry is coupled to the first circuitry and is operable in a first mode to pass all of the plurality of bits of data received from the first circuitry and in a second mode has at least one word comprising selected ones of the plurality of bits, the selected ones of the bits having a bit order. The third circuitry is provided coupled to the second circuitry and operable to pass all of the bits of data received from the second circuitry in the first mode and operable to selectively reverse the ordering of the selected ones of the bits and pass be at least one word received from the second circuitry in the second mode. The fourth circuitry is further provided coupled to the third circuitry inoperable to receive bits of data passed from the circuitry and select for output as at least one word of true color data at least some of the bits.

Color palette device having big/little endian interfacing, systems and

A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.

Memory cell circuits, devices, systems and methods of operation

Output buffer circuits with controlled Miller effect capacitance

Capacitance compensation techniques are used to reduce capacitive effects that impact on the performance of current steering circuits (FIG. 1). In an isolation technique (FIGS. 2a-2e), a resistor (R) or a diode (D) is coupled to a data-switched transistor to dampen voltage perturbations associated with the gate-to-source capacitance. In a design variable technique FIGS. 3a-3d), a transistor (PDV) is included in either the output or ground legs of the current steering circuit to provide a design variable to counteract the capacitive effects of the associated data-switched (PDX/NDX) or voltage-controlled (PREF) transistor. In a bipolar substitution technique (FIG. 4), a data-switched bipolar transistor (QDX) is substituted for the data-switched MOS transistor, and made sufficiently small to significantly reduce junction capacitance. In addition, capacitive effects can be reduced by introducing fabrication alterations (FIGS. 5a-5b), such as fabrication layouts in which the source contact is made within a U-shaped gate (FIG. 5a), and in which moat perimeter is contoured (FIG. 5b) for minimal gate area consistent with standard gate/contact spacing requirements.

Growing community of inventors

Plano, TX, United States of America

Louis J Izzi