Cadence Design Systems, Inc.

Cadenee Design Systems, Inc.

Louis-Francois Tanguay

Guillaume Fortin

Jean-Francois Delage

Mathieu Gagnon

Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.

Data sampler with capacitive digital-to-analog converter

Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.)

Quarter-rate data sampling with loop-unrolled decision feedback equalization

Various embodiments provide for data sampling with loop-unrolled decision feedback equalization. In particular, some embodiments provide for an unrolled first-tap Decision Feedback Equalizer (DFE) loop that comprises parallel data samplers that each include a tri-state output.

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Montréal, Canada

Louis-Francois Tanguay