International Business Machines Corporation

Mellanox Technologies, Ltd.

Louis Bennie Capps, Jr

Michael Jay Shapiro

Robert H Bell, Jr

Ronald Edward Newhart

Thomas Edward Cook

Anand Haridass

Michael A Paolini

Glenn Graham Daves

Robert Christopher Dixon

Thoi Nguyen

Warren D Dyckman

An Xuan Tra

Jean Audet

Son Hung Lam

Aaron K Baughman

Luis Alfonso Lastras-Montano

Elad Mentovich

Naresh Nayar

Paraskevas Bakopoulos

Eitan Zahavi

Barry Michael Graham

Mark Elliott Hack

Steven Paul Hartman

Dimitrios Syrivelis

Richard Nicholas Iachetta, Jr

Scott Leonard Daniels

Warren E Price

Khuong Huu Pham

Jennifer R Mahle

Prethvi Ramesh Kashinkunti

Julie Irene Marcelle Bernauer

Joanne Ferris

Daniel Mark Dreps

Michael Richard Ouellette

Bruce Gerard Mealey

Danny Marvin Neal

Van Hoa Lee

Richard Bealkowski

William Elton Burky

Dimitrios Kalavrouziotis

Ioannis (Giannis) Patronas

Ralph M Begun

Bernadette Ann Pierson

John Blake Pavelka

Thomas J Dewkett

James Douglas Jordan

Philip E Milling

Yat Hung Ng

Nikolaos Argyris

Kenneth Allen Uplinger

Jimmy G Foster

Robert W Rupe

Darryl Edmond Judice

Danie M Dreps

Konstantinos Tokas

Josefina Santiago Drerup

Nikolaos Terzenidis

Systems, computer program products, and methods are described herein for dynamic reconfiguration of network communications. An example system includes a first network pod including a first set of network ports, a second network pod including a second set of network ports, a set of network cores, and a first intermediate network switch. The first intermediate switch operatively couples the first network pod, the second network pod, and the set of network cores. The first intermediate network switch is configured to selectively establish full bisectional bandwidth data communication between a subset of the set of network cores, a subset of the first set of network ports, and a subset of the second set of network ports.

Systems and methods for dynamic reconfiguration of network communications

Systems, computer program products, and methods are described herein for network discovery, port identification, and/or identifying fiber link failures in an optical network, in accordance with an embodiment of the invention. The present invention may be configured to sequentially connect each port of an optical switch to a network port of a server and generate, based on information associated with network devices connected to the ports, a network map. The network map may identify which network devices are connected to which ports of the optical switch and may permit dynamic port mapping for network installation, upgrades, repairs, and/or the like. The present invention may also be configured to determine a fiber link in which a failure occurred and reconfigure the optical switch to allow communication between an optical time-domain reflectometer and the fiber link to test the fiber link.

Systems and methods for identifying fiber link failures in an optical network

According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.

System, method and computer program product for data transfer management

A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.

Multicore processor and method of use that configures core functions based on executing instructions

According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a method of updating an expert corpus set, including obtaining a query from a user, obtaining a raw data source, determining a relevance score for the raw data source with respect to the query, by performing actions including creating a first vector of statistical variables for the query using at least one natural language processing (NLP) socket, the statistical variables having category types, creating a second vector for the first raw data source, having category types that are the same as those for the query and generating a hypothesis regarding the relevance of the raw data source, testing the hypothesis by comparing relative statistical variables, calculating a gradient between the vectors to determine the relevance score and updating the expert corpus set with the raw data in response to the relevance score exceeds a threshold.

System and method for an expert question answer system from a dynamic corpus

A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.

Dynamic instruction execution based on transaction priority tagging

A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Multicore processor and method of use that adapts core functions based on workload execution

A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict

A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.

Configuring plural cores to perform an instruction having a multi-core characteristic

Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution

Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.

Data and control encryption

Growing community of inventors

Georgetown, TX, United States of America

Louis Bennie Capps, Jr