Siemens Aktiengesellschaft

Infineon Technologies Ag

Qimonda Ag

Infineon Technologies Richmond, LP

Infineon Technologies North America Corp.

Lothar Risch

Franz Hofmann

Wolfgang Krautschneider

Wolfgang Roesner

Thomas Schulz

Wolfgang R&ouml;sner

Wolfgang Rosner

Ties Ramcke

Gerhard Enders

Dietrich Widmann

Thomas Aeugle

Wolfgang Rösner

Reinhard Tielert

Franz Hofman

Till Schloesser

Michael Specht

Richard Johannes Luyken

Dirk Manger

Ignaz Eisele

Harald Gossner

Karl Hofmann

Thomas Vogelsang

Thomas Happ

Peter Baars

Reinhard J Stengl

Stefan Tegen

Martin Franosch

Hans Reisinger

Siegfried Schwarzl

Rainer Bruchhaus

Till Schl&ouml;sser

Herbert Schäfer

Wolfram Wersing

Klaus Muemmler

Ulrike Gruening-von Schwerin

Erwin Hammerl

Matthias Ilg

Till Schlösser

Wolfgang Peter Mueller

Ingmar Feigt

Martin Bartels

Bernhard Lustig

Erich Pammer

Herbert Sch&auml;fer

Christoph Werner

Armin Wieder

Hermann Jacobs

Thomas &Auml;ugle

Paul-Werner Basse

Klaus Lau

Hermann Baumgaertner

Thomas Äugle

Karlheinz Friedrich

Hermann Mader

Thomas Schultz

An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Integrated circuit including a gate electrode

An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Integrated circuit including an array of memory cells and method

A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

DRAM memory cell

The invention relates to a transistor that is provided with a first source/drain area (S/D), a channel area (KA) adjacent thereto, a second source/drain area (S/D) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D) are arranged in the insulating area. The second source/drain area (S/D) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

DRAM cell structure with tunnel barrier

A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Method for producing a vertical semiconductor transistor component and vertical semiconductor transistor component

A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

Double gate MOSFET transistor and method for the production thereof

A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.

Nonvolatile semiconductor memory cell and method for fabricating the memory cell

A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 10 cm is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors

In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

Optoelectronic microelectronic system

An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.

Integrated CMOS circuit configuration, and production of same

A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Double gated transistor

A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.

Memory cell configuration, magnetic ram, and associative memory

A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Static random access memory (SRAM)

At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.

Circuit configuration having at least one nanoelectronic component and method for fabricating the component

Growing community of inventors

Neubiberg, Germany

Lothar Risch