Thomson Licensing

Lothar Freissmann

Tim Niggemeier

Thomas Brune

Marten Kabutz

Richard Rutschmann

The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.

Memory controller

A method and arrangement for using Synchronous Dynamic Random Access Memory (SDRAM) as storage for correction and track buffering in front end ICs of optical recording or reproduction devices. Data to be stored or read is organized in appropriate bursts for accelerating the SDRAM (SDR) traffic. The SDRAM is built around two banks of memory, and are accessed using a pipelined address logic, thereby accelerating access speeds.

Usage of an SDRAM as storage for correction and track buffering in frontend ICs of optical recording or reproduction devices

The present invention relates to a method and an arrangement for preparation of data for a Reed-Solomon decoder and more particularly to a method and an arrangement for an intelligent buffer in front of a ramless DVD Reed-Solomon decoder and further on particularly to a method and an arrangement for an intelligent buffer used also as a first pass correction storage of ECC-blocks. In such a way, the Reed-Solomon decoder will not get disordered ECC blocks by an intelligent buffer that leads to less necessary RAM and a high performance of the complete circuitry. The intelligent buffer is used as a first pass correction storage of the Reed Solomon decoder too.

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Niedereschach, Germany

Lothar Freissmann