International Business Machines Corporation

Texas Instruments Corporation

Globalfoundries Inc.

Lothar Felten

Joerg H Walter

Lars Lotzenburger

Norbert Schumacher

Joerg Deutschle

Volker Urban

Christopher S Smith

Klaus Keuerleber

Ulrike Schmidt

Ursel Hahn

Marcel Naggatz

The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model within a register transfer level, providing a filtering algorithm or filtering rules for signals occurring in the HDL or VHDL hardware description model, extracting signals from the HDL or VHDL hardware description model according to said filtering algorithm or filtering rules in order to get relevant signals, performing a simulation process of the HDL or VHDL hardware description model, performing a checking routine for the relevant signals in every cycle and storing and/or cumulating the relevant signals in a data base. Further the present invention relates to a corresponding system.

Generating coverage data for a switch frequency of HDL or VHDL signals

A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit is coupled to the bus and is arranged to transmit communications across the bus during an active period of the bus and to initiate communications during (and/or at the end of) a quiescent period of the bus. A slave unit is coupled to the bus and is arranged to couple power from the one or more signal lines to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus.

Bus pin reduction and power management

A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Dynamic prescaling counters

A method for simulating an operation of a digital circuit () is described. The method utilizes cycle simulation, wherein in a cycle based simulation model () of the digital circuit () components () of the digital circuit () are clocked synchronously every cycle () of a functional clock (Clk). According to the invention, real digital circuit (), i.e. chip or combinatorial logic (), timing information is included in the cycle simulation by inserting delay latches () into the cycle based simulation model () of the digital circuit (), wherein a non-functional clock (Sim clock) is used to clock the delay latches (), so that each delay latch () delays the propagation of a signal (I, J, K) by a cycle () of the non-functional clock (Sim clock).

Simulating an operation of a digital circuit

The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.

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Hauset, Belgium

Lothar Felten