Stmicroelectronics S.r.l.

Other

Ovonyx Inc.

Loris Vendrame

Fabio Pellizzer

Augusto Benvenuti

Tyler A Lowrey

Roberto Gastaldi

Giulio Casagrande

Paolo Ghezzi

Ferdinando Bedeschi

Paolo Giuseppe Cappelletti

Alfonso Maurelli

Giorgio Oddone

Paola Zuliani

Paolo Caprara

Antonio Barcella

Paola Zabberoni

Luca Bortesi

Alessandro Bogliolo

A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

Process for manufacturing an array of cells including selection bipolar junction transistors

A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

Memory device with unipolar and bipolar selectors

A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit currents that affect known test structures, and allows a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

Method and relative test structure for measuring the coupling capacitance between two interconnect lines

An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Electrically erasable and programmable non-volatile memory cell

A transistor includes a substrate region ( ) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region ( ) of the first type (P&plus;) of conductivity inside the substrate region ( ) and adjacent to a first terminal (C) of the transistor, a well ( ) of second type (N) of conductivity placed inside the substrate region ( ), wherein the well ( ) of second type (N) of conductivity includes at least a second contact region ( ) of a second type of conductivity (N&plus;) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions ( ) of the first type of conductivity (P&plus;) adjacent to a plurality of regions of a third terminal (E , . . . , E ) of the transistor interposed each one ( ) and other ( ) by proper insulating shapes ( ).

Multi-emitter bipolar transistor for bandgap reference circuits

A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor. The bipolar transistor includes: a buried semiconductor layer having a second type of conductivity placed at a prescribed depth from the surface of said bipolar transistor, an isolation semiconductor region having the second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate, forming a base region; an emitter region formed within said base region having the second type of conductivity, a base contact region of said transistor formed within said base region having the first type of conductivity, a collector contact region formed within said isolation semiconductor region having the second type of conductivity, wherein said base region has a doping concentration between 10 and 10 atoms/cm .

Bipolar transistor produced using processes compatible with those employed in the manufacture of MOS device

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Carbonera, Italy

Loris Vendrame